urcu-bp: use sys_membarrier when available
[urcu.git] / urcu / arch / x86.h
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1#ifndef _URCU_ARCH_X86_H
2#define _URCU_ARCH_X86_H
121a5d44 3
6d0ce021 4/*
af02d47e 5 * arch_x86.h: trivial definitions for the x86 architecture.
6d0ce021 6 *
af02d47e 7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
6982d6d7 8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
6d0ce021 9 *
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10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
05dd4b94 14 *
af02d47e 15 * This library is distributed in the hope that it will be useful,
6d0ce021 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
6d0ce021 19 *
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20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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23 */
24
ec4e58a3 25#include <urcu/compiler.h>
c96a3726 26#include <urcu/config.h>
121a5d44 27
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28#ifdef __cplusplus
29extern "C" {
30#endif
31
06f22bdb 32#define CAA_CACHE_LINE_SIZE 128
b4e52e3e 33
02be5561 34#ifdef CONFIG_RCU_HAVE_FENCE
e51500ed 35#define cmm_mb() __asm__ __volatile__ ("mfence":::"memory")
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36
37/*
38 * Define cmm_rmb/cmm_wmb to "strict" barriers that may be needed when
39 * using SSE or working with I/O areas. cmm_smp_rmb/cmm_smp_wmb are
40 * only compiler barriers, which is enough for general use.
41 */
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42#define cmm_rmb() __asm__ __volatile__ ("lfence":::"memory")
43#define cmm_wmb() __asm__ __volatile__ ("sfence"::: "memory")
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44#define cmm_smp_rmb() cmm_barrier()
45#define cmm_smp_wmb() cmm_barrier()
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46#else
47/*
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48 * We leave smp_rmb/smp_wmb as full barriers for processors that do not have
49 * fence instructions.
50 *
51 * An empty cmm_smp_rmb() may not be enough on old PentiumPro multiprocessor
52 * systems, due to an erratum. The Linux kernel says that "Even distro
53 * kernels should think twice before enabling this", but for now let's
54 * be conservative and leave the full barrier on 32-bit processors. Also,
55 * IDT WinChip supports weak store ordering, and the kernel may enable it
56 * under our feet; cmm_smp_wmb() ceases to be a nop for these processors.
6d0ce021 57 */
b33e85a8 58#if (CAA_BITS_PER_LONG == 32)
e51500ed 59#define cmm_mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
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60#define cmm_rmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
61#define cmm_wmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
62#else
63#define cmm_mb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
64#define cmm_rmb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
65#define cmm_wmb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
66#endif
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67#endif
68
2c81778b 69#define caa_cpu_relax() __asm__ __volatile__ ("rep; nop" : : : "memory")
6d0ce021 70
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71#define rdtscll(val) \
72 do { \
73 unsigned int __a, __d; \
e51500ed 74 __asm__ __volatile__ ("rdtsc" : "=a" (__a), "=d" (__d)); \
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75 (val) = ((unsigned long long)__a) \
76 | (((unsigned long long)__d) << 32); \
77 } while(0)
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78
79typedef unsigned long long cycles_t;
80
06f22bdb 81static inline cycles_t caa_get_cycles(void)
6d0ce021 82{
af02d47e 83 cycles_t ret = 0;
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84
85 rdtscll(ret);
86 return ret;
87}
121a5d44 88
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89#ifdef __cplusplus
90}
91#endif
92
1b9119f8 93#include <urcu/arch/generic.h>
e4d1eb09 94
ec4e58a3 95#endif /* _URCU_ARCH_X86_H */
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