[urcu.git] / urcu / arch / x86.h

#ifndef _URCU_ARCH_X86_H
#define _URCU_ARCH_X86_H

/*
 * arch_x86.h: trivial definitions for the x86 architecture.
 *
 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 */

#include <urcu/compiler.h>
#include <urcu/config.h>

#ifdef __cplusplus
extern "C" {
#endif 

#define CAA_CACHE_LINE_SIZE	128

#ifdef CONFIG_RCU_HAVE_FENCE
#define cmm_mb()    asm volatile("mfence":::"memory")
#define cmm_rmb()   asm volatile("lfence":::"memory")
#define cmm_wmb()   asm volatile("sfence"::: "memory")
#else
/*
 * Some non-Intel clones support out of order store. cmm_wmb() ceases to be a
 * nop for these.
 */
#define cmm_mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
#define cmm_rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
#define cmm_wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
#endif

#define caa_cpu_relax()	asm volatile("rep; nop" : : : "memory");

#define rdtscll(val)							  \
	do {						  		  \
	     unsigned int __a, __d;					  \
	     asm volatile("rdtsc" : "=a" (__a), "=d" (__d));		  \
	     (val) = ((unsigned long long)__a)				  \
			| (((unsigned long long)__d) << 32);		  \
	} while(0)

typedef unsigned long long cycles_t;

static inline cycles_t caa_get_cycles(void)
{
        cycles_t ret = 0;

        rdtscll(ret);
        return ret;
}

#ifdef __cplusplus 
}
#endif

#include <urcu/arch/generic.h>

#endif /* _URCU_ARCH_X86_H */
Commit	Line	Data
ec4e58a3 MD	1	#ifndef _URCU_ARCH_X86_H
ec4e58a3 MD	2	#define _URCU_ARCH_X86_H
121a5d44	3
6d0ce021	4	/*
af02d47e	5	* arch_x86.h: trivial definitions for the x86 architecture.
6d0ce021	6	*
af02d47e	7	* Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
6982d6d7	8	* Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
6d0ce021	9	*
af02d47e MD	10	* This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU Lesser General Public
	12	* License as published by the Free Software Foundation; either
	13	* version 2.1 of the License, or (at your option) any later version.
05dd4b94	14	*
af02d47e	15	* This library is distributed in the hope that it will be useful,
6d0ce021	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
af02d47e MD	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
af02d47e MD	18	* Lesser General Public License for more details.
6d0ce021	19	*
af02d47e MD	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
6d0ce021 PM	23	*/
6d0ce021 PM	24
ec4e58a3	25	#include <urcu/compiler.h>
c96a3726	26	#include <urcu/config.h>
121a5d44	27
36bc70a8 MD	28	#ifdef __cplusplus
	29	extern "C" {
	30	#endif
	31
06f22bdb	32	#define CAA_CACHE_LINE_SIZE 128
b4e52e3e	33
02be5561	34	#ifdef CONFIG_RCU_HAVE_FENCE
5481ddb3 DG	35	#define cmm_mb() asm volatile("mfence":::"memory")
	36	#define cmm_rmb() asm volatile("lfence":::"memory")
	37	#define cmm_wmb() asm volatile("sfence"::: "memory")
6d0ce021 PM	38	#else
6d0ce021 PM	39	/*
5481ddb3	40	* Some non-Intel clones support out of order store. cmm_wmb() ceases to be a
6d0ce021 PM	41	* nop for these.
6d0ce021 PM	42	*/
5481ddb3 DG	43	#define cmm_mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
	44	#define cmm_rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
	45	#define cmm_wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
6d0ce021 PM	46	#endif
6d0ce021 PM	47
06f22bdb	48	#define caa_cpu_relax() asm volatile("rep; nop" : : : "memory");
6d0ce021	49
af02d47e MD	50	#define rdtscll(val) \
	51	do { \
	52	unsigned int __a, __d; \
	53	asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
	54	(val) = ((unsigned long long)__a) \
	55	\| (((unsigned long long)__d) << 32); \
	56	} while(0)
6d0ce021 PM	57
	58	typedef unsigned long long cycles_t;
	59
06f22bdb	60	static inline cycles_t caa_get_cycles(void)
6d0ce021	61	{
af02d47e	62	cycles_t ret = 0;
6d0ce021 PM	63
	64	rdtscll(ret);
	65	return ret;
	66	}
121a5d44	67
36bc70a8 MD	68	#ifdef __cplusplus
	69	}
	70	#endif
	71
1b9119f8	72	#include <urcu/arch/generic.h>
e4d1eb09	73
ec4e58a3	74	#endif /* _URCU_ARCH_X86_H */