s390 uatomic arch fix
[urcu.git] / urcu / arch_x86.h
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1#ifndef _URCU_ARCH_X86_H
2#define _URCU_ARCH_X86_H
121a5d44 3
6d0ce021 4/*
af02d47e 5 * arch_x86.h: trivial definitions for the x86 architecture.
6d0ce021 6 *
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7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
6d0ce021 9 *
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10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
14*
15 * This library is distributed in the hope that it will be useful,
6d0ce021 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
6d0ce021 19 *
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20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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23 */
24
ec4e58a3 25#include <urcu/compiler.h>
c96a3726 26#include <urcu/config.h>
121a5d44 27
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28#define CONFIG_HAVE_MEM_COHERENCY
29
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30#define CACHE_LINE_SIZE 128
31
49617de1 32#ifdef CONFIG_URCU_HAVE_FENCE
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33#define mb() asm volatile("mfence":::"memory")
34#define rmb() asm volatile("lfence":::"memory")
35#define wmb() asm volatile("sfence"::: "memory")
36#else
37/*
38 * Some non-Intel clones support out of order store. wmb() ceases to be a
39 * nop for these.
40 */
41#define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
42#define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
43#define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
44#endif
45
46/*
47 * Architectures without cache coherency need something like the following:
48 *
49 * #define mb() mc()
50 * #define rmb() rmc()
51 * #define wmb() wmc()
52 * #define mc() arch_cache_flush()
53 * #define rmc() arch_cache_flush_read()
54 * #define wmc() arch_cache_flush_write()
55 */
56
57#define mc() barrier()
58#define rmc() barrier()
59#define wmc() barrier()
60
49617de1 61#ifdef CONFIG_URCU_SMP
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62#define smp_mb() mb()
63#define smp_rmb() rmb()
64#define smp_wmb() wmb()
65#define smp_mc() mc()
66#define smp_rmc() rmc()
67#define smp_wmc() wmc()
68#else
69#define smp_mb() barrier()
70#define smp_rmb() barrier()
71#define smp_wmb() barrier()
72#define smp_mc() barrier()
73#define smp_rmc() barrier()
74#define smp_wmc() barrier()
75#endif
76
77/* Nop everywhere except on alpha. */
78#define smp_read_barrier_depends()
79
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80static inline void rep_nop(void)
81{
82 asm volatile("rep; nop" : : : "memory");
83}
84
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85static inline void cpu_relax(void)
86{
87 rep_nop();
88}
89
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90/*
91 * Serialize core instruction execution. Also acts as a compiler barrier.
92 */
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93#ifdef __PIC__
94/*
95 * Cannot use cpuid because it clobbers the ebx register and clashes
96 * with -fPIC :
97 * error: PIC register 'ebx' clobbered in 'asm'
98 */
99static inline void sync_core(void)
100{
101 mb();
102}
103#else
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104static inline void sync_core(void)
105{
106 asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
107}
5dba80f9 108#endif
ebb22fff 109
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110#define rdtscll(val) \
111 do { \
112 unsigned int __a, __d; \
113 asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
114 (val) = ((unsigned long long)__a) \
115 | (((unsigned long long)__d) << 32); \
116 } while(0)
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117
118typedef unsigned long long cycles_t;
119
af02d47e 120static inline cycles_t get_cycles(void)
6d0ce021 121{
af02d47e 122 cycles_t ret = 0;
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123
124 rdtscll(ret);
125 return ret;
126}
121a5d44 127
ec4e58a3 128#endif /* _URCU_ARCH_X86_H */
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