Support for sys_futex autodetection
[urcu.git] / urcu / arch_x86.h
CommitLineData
ec4e58a3
MD
1#ifndef _URCU_ARCH_X86_H
2#define _URCU_ARCH_X86_H
121a5d44 3
6d0ce021 4/*
af02d47e 5 * arch_x86.h: trivial definitions for the x86 architecture.
6d0ce021 6 *
af02d47e
MD
7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
6d0ce021 9 *
af02d47e
MD
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
14*
15 * This library is distributed in the hope that it will be useful,
6d0ce021 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
af02d47e
MD
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
6d0ce021 19 *
af02d47e
MD
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
6d0ce021
PM
23 */
24
ec4e58a3 25#include <urcu/compiler.h>
7d413817 26#include "config.h"
121a5d44 27
6d0ce021
PM
28#define CONFIG_HAVE_MEM_COHERENCY
29
b4e52e3e
MD
30#define CACHE_LINE_SIZE 128
31
af02d47e 32#ifndef BITS_PER_LONG
d2d23035 33#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
af02d47e
MD
34#endif
35
6d0ce021
PM
36#ifdef CONFIG_HAVE_FENCE
37#define mb() asm volatile("mfence":::"memory")
38#define rmb() asm volatile("lfence":::"memory")
39#define wmb() asm volatile("sfence"::: "memory")
40#else
41/*
42 * Some non-Intel clones support out of order store. wmb() ceases to be a
43 * nop for these.
44 */
45#define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
46#define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
47#define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
48#endif
49
50/*
51 * Architectures without cache coherency need something like the following:
52 *
53 * #define mb() mc()
54 * #define rmb() rmc()
55 * #define wmb() wmc()
56 * #define mc() arch_cache_flush()
57 * #define rmc() arch_cache_flush_read()
58 * #define wmc() arch_cache_flush_write()
59 */
60
61#define mc() barrier()
62#define rmc() barrier()
63#define wmc() barrier()
64
121a5d44
MD
65#ifdef CONFIG_SMP
66#define smp_mb() mb()
67#define smp_rmb() rmb()
68#define smp_wmb() wmb()
69#define smp_mc() mc()
70#define smp_rmc() rmc()
71#define smp_wmc() wmc()
72#else
73#define smp_mb() barrier()
74#define smp_rmb() barrier()
75#define smp_wmb() barrier()
76#define smp_mc() barrier()
77#define smp_rmc() barrier()
78#define smp_wmc() barrier()
79#endif
80
81/* Nop everywhere except on alpha. */
82#define smp_read_barrier_depends()
83
92d1c656
MD
84static inline void rep_nop(void)
85{
86 asm volatile("rep; nop" : : : "memory");
87}
88
6d0ce021
PM
89static inline void cpu_relax(void)
90{
91 rep_nop();
92}
93
ebb22fff
MD
94/*
95 * Serialize core instruction execution. Also acts as a compiler barrier.
96 */
5dba80f9
MD
97#ifdef __PIC__
98/*
99 * Cannot use cpuid because it clobbers the ebx register and clashes
100 * with -fPIC :
101 * error: PIC register 'ebx' clobbered in 'asm'
102 */
103static inline void sync_core(void)
104{
105 mb();
106}
107#else
ebb22fff
MD
108static inline void sync_core(void)
109{
110 asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
111}
5dba80f9 112#endif
ebb22fff 113
af02d47e
MD
114#define rdtscll(val) \
115 do { \
116 unsigned int __a, __d; \
117 asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
118 (val) = ((unsigned long long)__a) \
119 | (((unsigned long long)__d) << 32); \
120 } while(0)
6d0ce021
PM
121
122typedef unsigned long long cycles_t;
123
af02d47e 124static inline cycles_t get_cycles(void)
6d0ce021 125{
af02d47e 126 cycles_t ret = 0;
6d0ce021
PM
127
128 rdtscll(ret);
129 return ret;
130}
121a5d44 131
ec4e58a3 132#endif /* _URCU_ARCH_X86_H */
This page took 0.040978 seconds and 4 git commands to generate.