projects / urcu.git / blame
| Commit | Line | Data |
|---|---|---|
| ec4e58a3 MD |
1 | #ifndef _URCU_ARCH_X86_H |
| 2 | #define _URCU_ARCH_X86_H | |
| 121a5d44 | 3 | |
| 6d0ce021 | 4 | /* |
| af02d47e | 5 | * arch_x86.h: trivial definitions for the x86 architecture. |
| 6d0ce021 | 6 | * |
| af02d47e MD |
7 | * Copyright (c) 2009 Paul E. McKenney, IBM Corporation. |
| 8 | * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> | |
| 6d0ce021 | 9 | * |
| af02d47e MD |
10 | * This library is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU Lesser General Public | |
| 12 | * License as published by the Free Software Foundation; either | |
| 13 | * version 2.1 of the License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This library is distributed in the hope that it will be useful, | |
| 6d0ce021 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| af02d47e MD |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 18 | * Lesser General Public License for more details. | |
| 6d0ce021 | 19 | * |
| af02d47e MD |
20 | * You should have received a copy of the GNU Lesser General Public |
| 21 | * License along with this library; if not, write to the Free Software | |
| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA | |
| 6d0ce021 PM |
23 | */ |
| 24 | ||
| ec4e58a3 | 25 | #include <urcu/compiler.h> |
| c96a3726 | 26 | #include <urcu/config.h> |
| 121a5d44 | 27 | |
| 36bc70a8 MD |
28 | #ifdef __cplusplus |
| 29 | extern "C" { | |
| 30 | #endif | |
| 31 | ||
| b4e52e3e MD |
32 | #define CACHE_LINE_SIZE 128 |
| 33 | ||
| 02be5561 | 34 | #ifdef CONFIG_RCU_HAVE_FENCE |
| 6d0ce021 PM |
35 | #define mb() asm volatile("mfence":::"memory") |
| 36 | #define rmb() asm volatile("lfence":::"memory") | |
| 37 | #define wmb() asm volatile("sfence"::: "memory") | |
| 38 | #else | |
| 39 | /* | |
| 40 | * Some non-Intel clones support out of order store. wmb() ceases to be a | |
| 41 | * nop for these. | |
| 42 | */ | |
| 43 | #define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory") | |
| 44 | #define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory") | |
| 45 | #define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory") | |
| 46 | #endif | |
| 47 | ||
| e4d1eb09 | 48 | #define cpu_relax() asm volatile("rep; nop" : : : "memory"); |
| 6d0ce021 | 49 | |
| ebb22fff MD |
50 | /* |
| 51 | * Serialize core instruction execution. Also acts as a compiler barrier. | |
| e4d1eb09 | 52 | * Cannot use cpuid on PIC because it clobbers the ebx register; |
| 5dba80f9 MD |
53 | * error: PIC register 'ebx' clobbered in 'asm' |
| 54 | */ | |
| e4d1eb09 PB |
55 | #ifndef __PIC__ |
| 56 | #define sync_core() \ | |
| ebb22fff | 57 | asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx"); |
| 5dba80f9 | 58 | #endif |
| ebb22fff | 59 | |
| af02d47e MD |
60 | #define rdtscll(val) \ |
| 61 | do { \ | |
| 62 | unsigned int __a, __d; \ | |
| 63 | asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \ | |
| 64 | (val) = ((unsigned long long)__a) \ | |
| 65 | | (((unsigned long long)__d) << 32); \ | |
| 66 | } while(0) | |
| 6d0ce021 PM |
67 | |
| 68 | typedef unsigned long long cycles_t; | |
| 69 | ||
| af02d47e | 70 | static inline cycles_t get_cycles(void) |
| 6d0ce021 | 71 | { |
| af02d47e | 72 | cycles_t ret = 0; |
| 6d0ce021 PM |
73 | |
| 74 | rdtscll(ret); | |
| 75 | return ret; | |
| 76 | } | |
| 121a5d44 | 77 | |
| 36bc70a8 MD |
78 | #ifdef __cplusplus |
| 79 | } | |
| 80 | #endif | |
| 81 | ||
| e4d1eb09 PB |
82 | #include <urcu/arch_generic.h> |
| 83 | ||
| ec4e58a3 | 84 | #endif /* _URCU_ARCH_X86_H */ |