fix: handle EINTR correctly in get_cpu_mask_from_sysfs

[urcu.git] / include / urcu / static / urcu-mb.h

diff --git a/include/urcu/static/urcu-mb.h b/include/urcu/static/urcu-mb.h
index b97e42a6b5afc623a99149047a1f81e2301fa364..8ddbd0026cbcc129dd374fdf48a974a2bb4db665 100644 (file)
--- a/include/urcu/static/urcu-mb.h
+++ b/include/urcu/static/urcu-mb.h
@@ -1,31 +1,17 @@
+// SPDX-FileCopyrightText: 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
+// SPDX-FileCopyrightText: 2009 Paul E. McKenney, IBM Corporation.
+//
+// SPDX-License-Identifier: LGPL-2.1-or-later
+
 #ifndef _URCU_MB_STATIC_H
 #define _URCU_MB_STATIC_H
 
 /*
- * urcu-mb-static.h
- *
  * Userspace RCU header.
  *
  * TO BE INCLUDED ONLY IN CODE THAT IS TO BE RECOMPILED ON EACH LIBURCU
  * RELEASE. See urcu.h for linking dynamically with the userspace rcu library.
  *
- * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
- * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- *
  * IBM's contributions to this file may be relicensed under LGPLv2 or later.
  */
 
@@ -63,9 +49,9 @@ extern DECLARE_URCU_TLS(struct urcu_reader, urcu_mb_reader);
 
 /*
  * Helper for _urcu_mb_read_lock().  The format of urcu_mb_gp.ctr (as well as
- * the per-thread rcu_reader.ctr) has the upper bits containing a count of
- * _urcu_mb_read_lock() nesting, and a lower-order bit that contains either zero
- * or URCU_GP_CTR_PHASE.  The cmm_smp_mb() ensures that the accesses in
+ * the per-thread rcu_reader.ctr) has the lower-order bits containing a count of
+ * _urcu_mb_read_lock() nesting, and a single high-order URCU_BP_GP_CTR_PHASE bit
+ * that contains either zero or one.  The cmm_smp_mb() ensures that the accesses in
  * _urcu_mb_read_lock() happen before the subsequent read-side critical section.
  */
 static inline void _urcu_mb_read_lock_update(unsigned long tmp)
@@ -108,13 +94,14 @@ static inline void _urcu_mb_read_lock(void)
  */
 static inline void _urcu_mb_read_unlock_update_and_wakeup(unsigned long tmp)
 {
+       unsigned long *ctr = &URCU_TLS(urcu_mb_reader).ctr;
+
        if (caa_likely((tmp & URCU_GP_CTR_NEST_MASK) == URCU_GP_COUNT)) {
-               cmm_smp_mb();
-               _CMM_STORE_SHARED(URCU_TLS(urcu_mb_reader).ctr, tmp - URCU_GP_COUNT);
-               cmm_smp_mb();
+               uatomic_store(ctr, tmp - URCU_GP_COUNT, CMM_SEQ_CST);
                urcu_common_wake_up_gp(&urcu_mb_gp);
-       } else
-               _CMM_STORE_SHARED(URCU_TLS(urcu_mb_reader).ctr, tmp - URCU_GP_COUNT);
+       } else {
+               uatomic_store(ctr, tmp - URCU_GP_COUNT, CMM_RELAXED);
+       }
 }
 
 /*