define CACHE_LINE_SIZE in arch_*.h

[urcu.git] / urcu / arch_ppc.h

diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h
index 8dfd6d161970432a2225082295a424249af4b980..aaf61d30f03e7749823f0aff154987a07398e071 100644 (file)
--- a/urcu/arch_ppc.h
+++ b/urcu/arch_ppc.h
@@ -28,6 +28,9 @@
 #define CONFIG_HAVE_FENCE 1
 #define CONFIG_HAVE_MEM_COHERENCY
 
+/* Include size of POWER5+ L3 cache lines: 256 bytes */
+#define CACHE_LINE_SIZE        256
+
 #ifndef BITS_PER_LONG
 #define BITS_PER_LONG  (__SIZEOF_LONG__ * 8)
 #endif