define CACHE_LINE_SIZE in arch_*.h

[urcu.git] / tests / test_qsbr.c

diff --git a/tests/test_qsbr.c b/tests/test_qsbr.c
index cf2fec2a8cbc8ce19f366ce669412bf3842ef5f5..6230510ab39688d9ba8524e6aadc9bc721470883 100644 (file)
--- a/tests/test_qsbr.c
+++ b/tests/test_qsbr.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384