X-Git-Url: https://git.liburcu.org/?p=lttng-modules.git;a=blobdiff_plain;f=src%2Flib%2Fringbuffer%2Fring_buffer_frontend.c;fp=src%2Flib%2Fringbuffer%2Fring_buffer_frontend.c;h=fbf3a16837c8574ebf6b90a2986d804626ba2d97;hp=5316b7ff407196115726c2e33530978e17111b08;hb=18fd64422b4297f9beea82f1c1a97b80791312e4;hpb=217bc2e4685050dddce9bdd2557b64f6b8c16622

diff --git a/src/lib/ringbuffer/ring_buffer_frontend.c b/src/lib/ringbuffer/ring_buffer_frontend.c
index 5316b7ff..fbf3a168 100644
--- a/src/lib/ringbuffer/ring_buffer_frontend.c
+++ b/src/lib/ringbuffer/ring_buffer_frontend.c
@@ -1210,6 +1210,16 @@ static void lib_ring_buffer_flush_read_subbuf_dcache(
 	if (config->output != RING_BUFFER_MMAP)
 		return;
 
+#ifdef cpu_dcache_is_aliasing
+	/*
+	 * Some architectures implement flush_dcache_page() but don't
+	 * actually have aliasing dcache. cpu_dcache_is_aliasing() was
+	 * introduced in kernel v6.9 to query this more precisely.
+	 */
+	if (!cpu_dcache_is_aliasing())
+		return;
+#endif
+
 	/*
 	 * Architectures with caches aliased on virtual addresses may
 	 * use different cache lines for the linear mapping vs