X-Git-Url: https://git.liburcu.org/?a=blobdiff_plain;f=include%2Furcu%2Fuatomic%2Floongarch.h;h=3454d41294af3ae03721d903f43d77e0adff1534;hb=HEAD;hp=f41302a274920dd2534756727880ddf0905f3821;hpb=dc46a9c324ae94d89da41ea9a3f97503115df88e;p=urcu.git

diff --git a/include/urcu/uatomic/loongarch.h b/include/urcu/uatomic/loongarch.h
index f41302a..3454d41 100644
--- a/include/urcu/uatomic/loongarch.h
+++ b/include/urcu/uatomic/loongarch.h
@@ -1,28 +1,12 @@
+// SPDX-FileCopyrightText: 2021 Wang Jing <wangjing@loongson.cn>
+//
+// SPDX-License-Identifier: MIT
+
 #ifndef _URCU_UATOMIC_ARCH_LOONGARCH_H
 #define _URCU_UATOMIC_ARCH_LOONGARCH_H
 
 /*
  * Atomic exchange operations for the LoongArch architecture. Let GCC do it.
- *
- * Copyright (c) 2021 Wang Jing <wangjing@loongson.cn>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
  */
 
 #include <urcu/compiler.h>
@@ -32,6 +16,11 @@
 extern "C" {
 #endif
 
+/*
+ * LoongArch implements byte and short atomics with LL/SC instructions,
+ * which retry if the cache line is modified concurrently between LL and
+ * SC.
+ */
 #define UATOMIC_HAS_ATOMIC_BYTE
 #define UATOMIC_HAS_ATOMIC_SHORT