*/
#include <urcu/compiler.h>
-#include "config.h"
+#include <urcu/config.h>
-#define CONFIG_HAVE_MEM_COHERENCY
+#ifdef __cplusplus
+extern "C" {
+#endif
#define CACHE_LINE_SIZE 128
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
-#endif
-
-#ifdef CONFIG_HAVE_FENCE
+#ifdef CONFIG_RCU_HAVE_FENCE
#define mb() asm volatile("mfence":::"memory")
#define rmb() asm volatile("lfence":::"memory")
#define wmb() asm volatile("sfence"::: "memory")
#define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
#endif
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb() mc()
- * #define rmb() rmc()
- * #define wmb() wmc()
- * #define mc() arch_cache_flush()
- * #define rmc() arch_cache_flush_read()
- * #define wmc() arch_cache_flush_write()
- */
-
-#define mc() barrier()
-#define rmc() barrier()
-#define wmc() barrier()
-
-#ifdef CONFIG_SMP
-#define smp_mb() mb()
-#define smp_rmb() rmb()
-#define smp_wmb() wmb()
-#define smp_mc() mc()
-#define smp_rmc() rmc()
-#define smp_wmc() wmc()
-#else
-#define smp_mb() barrier()
-#define smp_rmb() barrier()
-#define smp_wmb() barrier()
-#define smp_mc() barrier()
-#define smp_rmc() barrier()
-#define smp_wmc() barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void rep_nop(void)
-{
- asm volatile("rep; nop" : : : "memory");
-}
-
-static inline void cpu_relax(void)
-{
- rep_nop();
-}
+#define cpu_relax() asm volatile("rep; nop" : : : "memory");
/*
* Serialize core instruction execution. Also acts as a compiler barrier.
+ * On PIC ebx cannot be clobbered
*/
#ifdef __PIC__
-/*
- * Cannot use cpuid because it clobbers the ebx register and clashes
- * with -fPIC :
- * error: PIC register 'ebx' clobbered in 'asm'
- */
-static inline void sync_core(void)
-{
- mb();
-}
-#else
-static inline void sync_core(void)
-{
+#define sync_core() \
+ asm volatile("push %%ebx; cpuid; pop %%ebx" \
+ : : : "memory", "eax", "ecx", "edx");
+#endif
+#ifndef __PIC__
+#define sync_core() \
asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
-}
#endif
#define rdtscll(val) \
return ret;
}
+#ifdef __cplusplus
+}
+#endif
+
+#include <urcu/arch_generic.h>
+
#endif /* _URCU_ARCH_X86_H */