* URCU_ARCH_ALPHA : All DEC Alpha variants
* URCU_ARCH_IA64 : All Intel Itanium variants
* URCU_ARCH_ARM : All ARM 32 bits variants
+ * URCU_ARCH_ARMV7 : All ARMv7 ISA variants
* URCU_ARCH_AARCH64 : All ARM 64 bits variants
* URCU_ARCH_MIPS : All MIPS variants
* URCU_ARCH_NIOS2 : All Intel / Altera NIOS II variants
#define URCU_ARCH_AMD64 1
#include <urcu/arch/x86.h>
-#elif (defined(__i486__) || defined(__i586__) || defined(__i686__))
-
-#define URCU_ARCH_X86 1
-#include <urcu/arch/x86.h>
-
#elif (defined(__i386__) || defined(__i386))
#define URCU_ARCH_X86 1
+
+/*
+ * URCU_ARCH_X86_NO_CAS enables a compat layer that will detect the presence of
+ * the cmpxchg instructions at runtime and provide a compat mode based on a
+ * pthread mutex when it isn't.
+ *
+ * __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 was introduced in GCC 4.3 and Clang 3.3,
+ * building with older compilers will result in the compat layer always being
+ * used on x86-32.
+ */
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#define URCU_ARCH_X86_NO_CAS 1
+/* For backwards compat */
#define URCU_ARCH_I386 1
+#endif
+
#include <urcu/arch/x86.h>
#elif (defined(__powerpc64__) || defined(__ppc64__))
#define URCU_ARCH_IA64 1
#include <urcu/arch/ia64.h>
+#elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__))
+
+#define URCU_ARCH_ARMV7 1
+#define URCU_ARCH_ARM 1
+#include <urcu/arch/arm.h>
+
#elif (defined(__arm__) || defined(__arm))
#define URCU_ARCH_ARM 1