d72cbf61ac1df31d62a8c7a2fe00895d55216d9d
[urcu.git] / urcu.h
1 #ifndef _URCU_H
2 #define _URCU_H
3
4 /*
5 * urcu.h
6 *
7 * Userspace RCU header
8 *
9 * Copyright February 2009 - Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
10 *
11 * Credits for Paul e. McKenney <paulmck@linux.vnet.ibm.com>
12 * for inspiration coming from the Linux kernel RCU and rcu-preempt.
13 *
14 * The barrier, mb, rmb, wmb, atomic_inc, smp_read_barrier_depends, ACCESS_ONCE
15 * and rcu_dereference primitives come from the Linux kernel.
16 *
17 * Distributed under GPLv2
18 */
19
20 #include <stdlib.h>
21 #include <pthread.h>
22
23 /* The "volatile" is due to gcc bugs */
24 #define barrier() __asm__ __volatile__("": : :"memory")
25
26 #define likely(x) __builtin_expect(!!(x), 1)
27 #define unlikely(x) __builtin_expect(!!(x), 0)
28
29 /*
30 * Assume the architecture has coherent caches. Blackfin will want this unset.
31 */
32 #define CONFIG_HAVE_MEM_COHERENCY 1
33
34 /* Assume P4 or newer */
35 #define CONFIG_HAVE_FENCE 1
36
37 /* Assume SMP machine, given we don't have this information */
38 #define CONFIG_SMP 1
39
40
41 #ifdef CONFIG_HAVE_MEM_COHERENCY
42 /*
43 * Caches are coherent, no need to flush them.
44 */
45 #define mc() barrier()
46 #define rmc() barrier()
47 #define wmc() barrier()
48 #else
49 #error "The architecture must create its own cache flush primitives"
50 #define mc() arch_cache_flush()
51 #define rmc() arch_cache_flush_read()
52 #define wmc() arch_cache_flush_write()
53 #endif
54
55
56 #ifdef CONFIG_HAVE_MEM_COHERENCY
57
58 /* x86 32/64 specific */
59 #ifdef CONFIG_HAVE_FENCE
60 #define mb() asm volatile("mfence":::"memory")
61 #define rmb() asm volatile("lfence":::"memory")
62 #define wmb() asm volatile("sfence"::: "memory")
63 #else
64 /*
65 * Some non-Intel clones support out of order store. wmb() ceases to be a
66 * nop for these.
67 */
68 #define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
69 #define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
70 #define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
71 #endif
72
73 #else /* !CONFIG_HAVE_MEM_COHERENCY */
74
75 /*
76 * Without cache coherency, the memory barriers become cache flushes.
77 */
78 #define mb() mc()
79 #define rmb() rmc()
80 #define wmb() wmc()
81
82 #endif /* !CONFIG_HAVE_MEM_COHERENCY */
83
84
85 #ifdef CONFIG_SMP
86 #define smp_mb() mb()
87 #define smp_rmb() rmb()
88 #define smp_wmb() wmb()
89 #define smp_mc() mc()
90 #define smp_rmc() rmc()
91 #define smp_wmc() wmc()
92 #else
93 #define smp_mb() barrier()
94 #define smp_rmb() barrier()
95 #define smp_wmb() barrier()
96 #define smp_mc() barrier()
97 #define smp_rmc() barrier()
98 #define smp_wmc() barrier()
99 #endif
100
101 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
102 static inline void rep_nop(void)
103 {
104 asm volatile("rep; nop" ::: "memory");
105 }
106
107 static inline void cpu_relax(void)
108 {
109 rep_nop();
110 }
111
112 static inline void atomic_inc(int *v)
113 {
114 asm volatile("lock; incl %0"
115 : "+m" (*v));
116 }
117
118 #define xchg(ptr, v) \
119 ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), sizeof(*(ptr))))
120
121 struct __xchg_dummy {
122 unsigned long a[100];
123 };
124 #define __xg(x) ((struct __xchg_dummy *)(x))
125
126 /*
127 * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
128 * Note 2: xchg has side effect, so that attribute volatile is necessary,
129 * but generally the primitive is invalid, *ptr is output argument. --ANK
130 * x is considered local, ptr is considered remote.
131 */
132 static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
133 int size)
134 {
135 switch (size) {
136 case 1:
137 asm volatile("xchgb %b0,%1"
138 : "=q" (x)
139 : "m" (*__xg(ptr)), "0" (x)
140 : "memory");
141 break;
142 case 2:
143 asm volatile("xchgw %w0,%1"
144 : "=r" (x)
145 : "m" (*__xg(ptr)), "0" (x)
146 : "memory");
147 break;
148 case 4:
149 asm volatile("xchgl %k0,%1"
150 : "=r" (x)
151 : "m" (*__xg(ptr)), "0" (x)
152 : "memory");
153 break;
154 case 8:
155 asm volatile("xchgq %0,%1"
156 : "=r" (x)
157 : "m" (*__xg(ptr)), "0" (x)
158 : "memory");
159 break;
160 }
161 smp_wmc();
162 return x;
163 }
164
165 /* Nop everywhere except on alpha. */
166 #define smp_read_barrier_depends()
167
168 /*
169 * Prevent the compiler from merging or refetching accesses. The compiler
170 * is also forbidden from reordering successive instances of ACCESS_ONCE(),
171 * but only when the compiler is aware of some particular ordering. One way
172 * to make the compiler aware of ordering is to put the two invocations of
173 * ACCESS_ONCE() in different C statements.
174 *
175 * This macro does absolutely -nothing- to prevent the CPU from reordering,
176 * merging, or refetching absolutely anything at any time. Its main intended
177 * use is to mediate communication between process-level code and irq/NMI
178 * handlers, all running on the same CPU.
179 */
180 #define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
181
182 /*
183 * Load a data from remote memory, doing a cache flush if required.
184 */
185 #define LOAD_REMOTE(p) ({ \
186 smp_rmc(); \
187 typeof(p) _________p1 = ACCESS_ONCE(p); \
188 (_________p1); \
189 })
190
191 /*
192 * Store v into x, where x is located in remote memory. Performs the required
193 * cache flush after writing.
194 */
195 #define STORE_REMOTE(x, v) \
196 do { \
197 (x) = (v); \
198 smp_wmc; \
199 } while (0)
200
201 /**
202 * rcu_dereference - fetch an RCU-protected pointer in an
203 * RCU read-side critical section. This pointer may later
204 * be safely dereferenced.
205 *
206 * Inserts memory barriers on architectures that require them
207 * (currently only the Alpha), and, more importantly, documents
208 * exactly which pointers are protected by RCU.
209 */
210
211 #define rcu_dereference(p) ({ \
212 typeof(p) _________p1 = LOAD_REMOTE(p); \
213 smp_read_barrier_depends(); \
214 (_________p1); \
215 })
216
217
218
219 #define SIGURCU SIGUSR1
220
221 /*
222 * If a reader is really non-cooperative and refuses to commit its
223 * urcu_active_readers count to memory (there is no barrier in the reader
224 * per-se), kick it after a few loops waiting for it.
225 */
226 #define KICK_READER_LOOPS 10000
227
228 #ifdef DEBUG_YIELD
229 #include <sched.h>
230 #include <time.h>
231 #include <pthread.h>
232 #include <unistd.h>
233
234 #define YIELD_READ (1 << 0)
235 #define YIELD_WRITE (1 << 1)
236
237 /* Updates without DEBUG_FULL_MB are much slower. Account this in the delay */
238 #ifdef DEBUG_FULL_MB
239 /* maximum sleep delay, in us */
240 #define MAX_SLEEP 50
241 #else
242 #define MAX_SLEEP 30000
243 #endif
244
245 extern unsigned int yield_active;
246 extern unsigned int __thread rand_yield;
247
248 static inline void debug_yield_read(void)
249 {
250 if (yield_active & YIELD_READ)
251 if (rand_r(&rand_yield) & 0x1)
252 usleep(rand_r(&rand_yield) % MAX_SLEEP);
253 }
254
255 static inline void debug_yield_write(void)
256 {
257 if (yield_active & YIELD_WRITE)
258 if (rand_r(&rand_yield) & 0x1)
259 usleep(rand_r(&rand_yield) % MAX_SLEEP);
260 }
261
262 static inline void debug_yield_init(void)
263 {
264 rand_yield = time(NULL) ^ pthread_self();
265 }
266 #else
267 static inline void debug_yield_read(void)
268 {
269 }
270
271 static inline void debug_yield_write(void)
272 {
273 }
274
275 static inline void debug_yield_init(void)
276 {
277
278 }
279 #endif
280
281 #ifdef DEBUG_FULL_MB
282 static inline void reader_barrier()
283 {
284 smp_mb();
285 }
286 #else
287 static inline void reader_barrier()
288 {
289 barrier();
290 }
291 #endif
292
293 /*
294 * The trick here is that RCU_GP_CTR_BIT must be a multiple of 8 so we can use a
295 * full 8-bits, 16-bits or 32-bits bitmask for the lower order bits.
296 */
297 #define RCU_GP_COUNT (1UL << 0)
298 /* Use the amount of bits equal to half of the architecture long size */
299 #define RCU_GP_CTR_BIT (1UL << (sizeof(long) << 2))
300 #define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
301
302 /*
303 * Global quiescent period counter with low-order bits unused.
304 * Using a int rather than a char to eliminate false register dependencies
305 * causing stalls on some architectures.
306 */
307 extern long urcu_gp_ctr;
308
309 extern long __thread urcu_active_readers;
310
311 static inline int rcu_old_gp_ongoing(long *value)
312 {
313 long v;
314
315 if (value == NULL)
316 return 0;
317 /*
318 * Make sure both tests below are done on the same version of *value
319 * to insure consistency.
320 */
321 v = LOAD_REMOTE(*value);
322 return (v & RCU_GP_CTR_NEST_MASK) &&
323 ((v ^ urcu_gp_ctr) & RCU_GP_CTR_BIT);
324 }
325
326 static inline void rcu_read_lock(void)
327 {
328 long tmp;
329
330 tmp = urcu_active_readers;
331 /* urcu_gp_ctr = RCU_GP_COUNT | (~RCU_GP_CTR_BIT or RCU_GP_CTR_BIT) */
332 /*
333 * The data dependency "read urcu_gp_ctr, write urcu_active_readers",
334 * serializes those two memory operations. We are not using STORE_REMOTE
335 * and LOAD_REMOTE here (although we should) because the writer will
336 * wake us up with a signal which does a flush in its handler to perform
337 * urcu_gp_ctr re-read and urcu_active_readers commit to main memory.
338 */
339 if (likely(!(tmp & RCU_GP_CTR_NEST_MASK)))
340 urcu_active_readers = ACCESS_ONCE(urcu_gp_ctr);
341 else
342 urcu_active_readers = tmp + RCU_GP_COUNT;
343 /*
344 * Increment active readers count before accessing the pointer.
345 * See force_mb_all_threads().
346 */
347 reader_barrier();
348 }
349
350 static inline void rcu_read_unlock(void)
351 {
352 reader_barrier();
353 /*
354 * Finish using rcu before decrementing the pointer.
355 * See force_mb_all_threads().
356 */
357 urcu_active_readers -= RCU_GP_COUNT;
358 }
359
360 /**
361 * rcu_assign_pointer - assign (publicize) a pointer to a newly
362 * initialized structure that will be dereferenced by RCU read-side
363 * critical sections. Returns the value assigned.
364 *
365 * Inserts memory barriers on architectures that require them
366 * (pretty much all of them other than x86), and also prevents
367 * the compiler from reordering the code that initializes the
368 * structure after the pointer assignment. More importantly, this
369 * call documents which pointers will be dereferenced by RCU read-side
370 * code.
371 */
372
373 #define rcu_assign_pointer(p, v) \
374 ({ \
375 if (!__builtin_constant_p(v) || \
376 ((v) != NULL)) \
377 wmb(); \
378 (p) = (v); \
379 smp_wmc(); \
380 })
381
382 #define rcu_xchg_pointer(p, v) \
383 ({ \
384 if (!__builtin_constant_p(v) || \
385 ((v) != NULL)) \
386 wmb(); \
387 xchg(p, v); \
388 })
389
390 extern void synchronize_rcu(void);
391
392 /*
393 * Exchanges the pointer and waits for quiescent state.
394 * The pointer returned can be freed.
395 */
396 #define urcu_publish_content(p, v) \
397 ({ \
398 void *oldptr; \
399 oldptr = rcu_xchg_pointer(p, v); \
400 synchronize_rcu(); \
401 oldptr; \
402 })
403
404 /*
405 * Reader thread registration.
406 */
407 extern void urcu_register_thread(void);
408 extern void urcu_unregister_thread(void);
409
410 #endif /* _URCU_H */
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