| 1 | #ifndef _ARCH_X86_H |
| 2 | #define _ARCH_X86_H |
| 3 | |
| 4 | /* |
| 5 | * arch_x86.h: trivial definitions for the x86 architecture. |
| 6 | * |
| 7 | * Copyright (c) 2009 Paul E. McKenney, IBM Corporation. |
| 8 | * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> |
| 9 | * |
| 10 | * This library is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU Lesser General Public |
| 12 | * License as published by the Free Software Foundation; either |
| 13 | * version 2.1 of the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This library is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 18 | * Lesser General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU Lesser General Public |
| 21 | * License along with this library; if not, write to the Free Software |
| 22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
| 23 | */ |
| 24 | |
| 25 | #include <compiler.h> |
| 26 | #include <arch_atomic.h> |
| 27 | |
| 28 | /* Assume P4 or newer */ |
| 29 | #define CONFIG_HAVE_FENCE 1 |
| 30 | #define CONFIG_HAVE_MEM_COHERENCY |
| 31 | |
| 32 | #ifndef BITS_PER_LONG |
| 33 | #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) |
| 34 | #endif |
| 35 | |
| 36 | #ifdef CONFIG_HAVE_FENCE |
| 37 | #define mb() asm volatile("mfence":::"memory") |
| 38 | #define rmb() asm volatile("lfence":::"memory") |
| 39 | #define wmb() asm volatile("sfence"::: "memory") |
| 40 | #else |
| 41 | /* |
| 42 | * Some non-Intel clones support out of order store. wmb() ceases to be a |
| 43 | * nop for these. |
| 44 | */ |
| 45 | #define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory") |
| 46 | #define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory") |
| 47 | #define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory") |
| 48 | #endif |
| 49 | |
| 50 | /* |
| 51 | * Architectures without cache coherency need something like the following: |
| 52 | * |
| 53 | * #define mb() mc() |
| 54 | * #define rmb() rmc() |
| 55 | * #define wmb() wmc() |
| 56 | * #define mc() arch_cache_flush() |
| 57 | * #define rmc() arch_cache_flush_read() |
| 58 | * #define wmc() arch_cache_flush_write() |
| 59 | */ |
| 60 | |
| 61 | #define mc() barrier() |
| 62 | #define rmc() barrier() |
| 63 | #define wmc() barrier() |
| 64 | |
| 65 | /* Assume SMP machine, given we don't have this information */ |
| 66 | #define CONFIG_SMP 1 |
| 67 | |
| 68 | #ifdef CONFIG_SMP |
| 69 | #define smp_mb() mb() |
| 70 | #define smp_rmb() rmb() |
| 71 | #define smp_wmb() wmb() |
| 72 | #define smp_mc() mc() |
| 73 | #define smp_rmc() rmc() |
| 74 | #define smp_wmc() wmc() |
| 75 | #else |
| 76 | #define smp_mb() barrier() |
| 77 | #define smp_rmb() barrier() |
| 78 | #define smp_wmb() barrier() |
| 79 | #define smp_mc() barrier() |
| 80 | #define smp_rmc() barrier() |
| 81 | #define smp_wmc() barrier() |
| 82 | #endif |
| 83 | |
| 84 | /* Nop everywhere except on alpha. */ |
| 85 | #define smp_read_barrier_depends() |
| 86 | |
| 87 | static inline void rep_nop(void) |
| 88 | { |
| 89 | asm volatile("rep; nop" : : : "memory"); |
| 90 | } |
| 91 | |
| 92 | static inline void cpu_relax(void) |
| 93 | { |
| 94 | rep_nop(); |
| 95 | } |
| 96 | |
| 97 | /* |
| 98 | * Serialize core instruction execution. Also acts as a compiler barrier. |
| 99 | */ |
| 100 | #ifdef __PIC__ |
| 101 | /* |
| 102 | * Cannot use cpuid because it clobbers the ebx register and clashes |
| 103 | * with -fPIC : |
| 104 | * error: PIC register 'ebx' clobbered in 'asm' |
| 105 | */ |
| 106 | static inline void sync_core(void) |
| 107 | { |
| 108 | mb(); |
| 109 | } |
| 110 | #else |
| 111 | static inline void sync_core(void) |
| 112 | { |
| 113 | asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx"); |
| 114 | } |
| 115 | #endif |
| 116 | |
| 117 | #define rdtscll(val) \ |
| 118 | do { \ |
| 119 | unsigned int __a, __d; \ |
| 120 | asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \ |
| 121 | (val) = ((unsigned long long)__a) \ |
| 122 | | (((unsigned long long)__d) << 32); \ |
| 123 | } while(0) |
| 124 | |
| 125 | typedef unsigned long long cycles_t; |
| 126 | |
| 127 | static inline cycles_t get_cycles(void) |
| 128 | { |
| 129 | cycles_t ret = 0; |
| 130 | |
| 131 | rdtscll(ret); |
| 132 | return ret; |
| 133 | } |
| 134 | |
| 135 | #endif /* _ARCH_X86_H */ |