| 1 | #ifndef _ARCH_ATOMIC_PPC_H |
| 2 | #define _ARCH_ATOMIC_PPC_H |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved. |
| 6 | * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved. |
| 7 | * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P. |
| 8 | * Copyright (c) 2009 Mathieu Desnoyers |
| 9 | * |
| 10 | * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED |
| 11 | * OR IMPLIED. ANY USE IS AT YOUR OWN RISK. |
| 12 | * |
| 13 | * Permission is hereby granted to use or copy this program |
| 14 | * for any purpose, provided the above notices are retained on all copies. |
| 15 | * Permission to modify the code and to distribute modified code is granted, |
| 16 | * provided the above notices are retained, and a notice that the code was |
| 17 | * modified is included with the above copyright notice. |
| 18 | * |
| 19 | * Code inspired from libatomic_ops-1.2, inherited in part from the |
| 20 | * Boehm-Demers-Weiser conservative garbage collector. |
| 21 | */ |
| 22 | |
| 23 | #ifndef __SIZEOF_LONG__ |
| 24 | #ifdef __powerpc64__ |
| 25 | #define __SIZEOF_LONG__ 8 |
| 26 | #else |
| 27 | #define __SIZEOF_LONG__ 4 |
| 28 | #endif |
| 29 | #endif |
| 30 | |
| 31 | #ifndef BITS_PER_LONG |
| 32 | #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) |
| 33 | #endif |
| 34 | |
| 35 | #define ILLEGAL_INSTR ".long 0xd00d00" |
| 36 | |
| 37 | #ifndef _INCLUDE_API_H |
| 38 | |
| 39 | /* |
| 40 | * Using a isync as second barrier for exchange to provide acquire semantic. |
| 41 | * According to atomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly |
| 42 | * explicit that this also has acquire semantics." |
| 43 | * Derived from AO_compare_and_swap(), but removed the comparison. |
| 44 | */ |
| 45 | |
| 46 | static __attribute__((always_inline)) |
| 47 | unsigned int atomic_exchange_32(volatile unsigned int *addr, unsigned int val) |
| 48 | { |
| 49 | unsigned int result; |
| 50 | |
| 51 | __asm__ __volatile__( |
| 52 | "lwsync\n" |
| 53 | "1:\t" "lwarx %0,0,%1\n" /* load and reserve */ |
| 54 | "stwcx. %2,0,%1\n" /* else store conditional */ |
| 55 | "bne- 1b\n" /* retry if lost reservation */ |
| 56 | "isync\n" |
| 57 | : "=&r"(result) |
| 58 | : "r"(addr), "r"(val) |
| 59 | : "memory", "cc"); |
| 60 | |
| 61 | return result; |
| 62 | } |
| 63 | |
| 64 | #if (BITS_PER_LONG == 64) |
| 65 | |
| 66 | static __attribute__((always_inline)) |
| 67 | unsigned long atomic_exchange_64(volatile unsigned long *addr, |
| 68 | unsigned long val) |
| 69 | { |
| 70 | unsigned long result; |
| 71 | |
| 72 | __asm__ __volatile__( |
| 73 | "lwsync\n" |
| 74 | "1:\t" "ldarx %0,0,%1\n" /* load and reserve */ |
| 75 | "stdcx. %2,0,%1\n" /* else store conditional */ |
| 76 | "bne- 1b\n" /* retry if lost reservation */ |
| 77 | "isync\n" |
| 78 | : "=&r"(result) |
| 79 | : "r"(addr), "r"(val) |
| 80 | : "memory", "cc"); |
| 81 | |
| 82 | return result; |
| 83 | } |
| 84 | |
| 85 | #endif |
| 86 | |
| 87 | static __attribute__((always_inline)) |
| 88 | unsigned long _atomic_exchange(volatile void *addr, unsigned long val, int len) |
| 89 | { |
| 90 | switch (len) { |
| 91 | case 4: return atomic_exchange_32(addr, val); |
| 92 | #if (BITS_PER_LONG == 64) |
| 93 | case 8: return atomic_exchange_64(addr, val); |
| 94 | #endif |
| 95 | } |
| 96 | /* generate an illegal instruction. Cannot catch this with linker tricks |
| 97 | * when optimizations are disabled. */ |
| 98 | __asm__ __volatile__(ILLEGAL_INSTR); |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | #define xchg(addr, v) (__typeof__(*(addr))) _atomic_exchange((addr), (v), \ |
| 103 | sizeof(*(addr))) |
| 104 | |
| 105 | #endif /* #ifndef _INCLUDE_API_H */ |
| 106 | |
| 107 | #endif /* ARCH_ATOMIC_PPC_H */ |