Update arch_s390.h, missing definitions
[urcu.git] / urcu / arch_sparc64.h
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1#ifndef _URCU_ARCH_SPARC64_H
2#define _URCU_ARCH_SPARC64_H
3
4/*
5 * arch_sparc64.h: trivial definitions for the Sparc64 architecture.
6 *
7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
14*
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24
25#include <urcu/compiler.h>
26#include <urcu/config.h>
27
28#define CONFIG_HAVE_MEM_COHERENCY
29
30#define CACHE_LINE_SIZE 256
31
32#ifndef BITS_PER_LONG
33#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
34#endif
35
36/*
37 * Inspired from the Linux kernel. Workaround Spitfire bug #51.
38 */
39#define membar_safe(type) \
40__asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
41 "membar " type "\n" \
42 "1:\n" \
43 : : : "memory")
44
45#define mb() membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
46#define rmb() membar_safe("#LoadLoad")
47#define wmb() membar_safe("#StoreStore")
48
49/*
50 * Architectures without cache coherency need something like the following:
51 *
52 * #define mb() mc()
53 * #define rmb() rmc()
54 * #define wmb() wmc()
55 * #define mc() arch_cache_flush()
56 * #define rmc() arch_cache_flush_read()
57 * #define wmc() arch_cache_flush_write()
58 */
59
60#define mc() barrier()
61#define rmc() barrier()
62#define wmc() barrier()
63
64#ifdef CONFIG_URCU_SMP
65#define smp_mb() mb()
66#define smp_rmb() rmb()
67#define smp_wmb() wmb()
68#define smp_mc() mc()
69#define smp_rmc() rmc()
70#define smp_wmc() wmc()
71#else
72#define smp_mb() barrier()
73#define smp_rmb() barrier()
74#define smp_wmb() barrier()
75#define smp_mc() barrier()
76#define smp_rmc() barrier()
77#define smp_wmc() barrier()
78#endif
79
80/* Nop everywhere except on alpha. */
81#define smp_read_barrier_depends()
82
83static inline void cpu_relax(void)
84{
85 barrier();
86}
87
88/*
89 * Serialize core instruction execution. Also acts as a compiler barrier.
90 */
91static inline void sync_core()
92{
93 mb();
94}
95
96typedef unsigned long long cycles_t;
97
98static inline cycles_t get_cycles (void)
99{
100 return 0; /* unimplemented */
101}
102
103#endif /* _URCU_ARCH_SPARC64_H */
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