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ec4e58a3 MD |
1 | #ifndef _URCU_ARCH_PPC_H |
2 | #define _URCU_ARCH_PPC_H | |
121a5d44 | 3 | |
6d0ce021 | 4 | /* |
af02d47e | 5 | * arch_ppc.h: trivial definitions for the powerpc architecture. |
6d0ce021 | 6 | * |
af02d47e | 7 | * Copyright (c) 2009 Paul E. McKenney, IBM Corporation. |
6982d6d7 | 8 | * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
6d0ce021 | 9 | * |
af02d47e MD |
10 | * This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2.1 of the License, or (at your option) any later version. | |
05dd4b94 | 14 | * |
af02d47e | 15 | * This library is distributed in the hope that it will be useful, |
6d0ce021 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
af02d47e MD |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
18 | * Lesser General Public License for more details. | |
6d0ce021 | 19 | * |
af02d47e MD |
20 | * You should have received a copy of the GNU Lesser General Public |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA | |
6d0ce021 PM |
23 | */ |
24 | ||
ec4e58a3 | 25 | #include <urcu/compiler.h> |
c96a3726 | 26 | #include <urcu/config.h> |
999991c6 | 27 | #include <urcu/syscall-compat.h> |
3fa18286 | 28 | #include <stdint.h> |
121a5d44 | 29 | |
36bc70a8 MD |
30 | #ifdef __cplusplus |
31 | extern "C" { | |
67ecffc0 | 32 | #endif |
36bc70a8 | 33 | |
b4e52e3e | 34 | /* Include size of POWER5+ L3 cache lines: 256 bytes */ |
06f22bdb | 35 | #define CAA_CACHE_LINE_SIZE 256 |
b4e52e3e | 36 | |
e62b2f86 MD |
37 | #ifdef __NO_LWSYNC__ |
38 | #define LWSYNC_OPCODE "sync\n" | |
39 | #else | |
40 | #define LWSYNC_OPCODE "lwsync\n" | |
41 | #endif | |
42 | ||
0174d10d PB |
43 | /* |
44 | * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not | |
45 | * preserve ordering of cacheable vs. non-cacheable accesses, so it | |
46 | * should not be used to order with respect to MMIO operations. An | |
47 | * eieio+lwsync pair is also not enough for cmm_rmb, because it will | |
48 | * order cacheable and non-cacheable memory operations separately---i.e. | |
49 | * not the latter against the former. | |
50 | */ | |
e51500ed | 51 | #define cmm_mb() __asm__ __volatile__ ("sync":::"memory") |
0174d10d PB |
52 | |
53 | /* | |
54 | * lwsync orders loads in cacheable memory with respect to other loads, | |
55 | * and stores in cacheable memory with respect to other stores. | |
56 | * Therefore, use it for barriers ordering accesses to cacheable memory | |
57 | * only. | |
58 | */ | |
e51500ed MD |
59 | #define cmm_smp_rmb() __asm__ __volatile__ (LWSYNC_OPCODE:::"memory") |
60 | #define cmm_smp_wmb() __asm__ __volatile__ (LWSYNC_OPCODE:::"memory") | |
6d0ce021 | 61 | |
af02d47e | 62 | #define mftbl() \ |
1b85da85 | 63 | __extension__ \ |
af02d47e MD |
64 | ({ \ |
65 | unsigned long rval; \ | |
e51500ed | 66 | __asm__ __volatile__ ("mftbl %0" : "=r" (rval)); \ |
af02d47e MD |
67 | rval; \ |
68 | }) | |
69 | ||
70 | #define mftbu() \ | |
1b85da85 | 71 | __extension__ \ |
af02d47e MD |
72 | ({ \ |
73 | unsigned long rval; \ | |
e51500ed | 74 | __asm__ __volatile__ ("mftbu %0" : "=r" (rval)); \ |
af02d47e MD |
75 | rval; \ |
76 | }) | |
6d0ce021 | 77 | |
9a9d403a | 78 | #define mftb() \ |
1b85da85 | 79 | __extension__ \ |
9a9d403a TMQMF |
80 | ({ \ |
81 | unsigned long long rval; \ | |
e51500ed | 82 | __asm__ __volatile__ ("mftb %0" : "=r" (rval)); \ |
9a9d403a TMQMF |
83 | rval; \ |
84 | }) | |
85 | ||
f8c43f45 MD |
86 | #define HAS_CAA_GET_CYCLES |
87 | ||
3fa18286 | 88 | typedef uint64_t caa_cycles_t; |
6d0ce021 | 89 | |
9a9d403a | 90 | #ifdef __powerpc64__ |
3fa18286 | 91 | static inline caa_cycles_t caa_get_cycles(void) |
6d0ce021 | 92 | { |
3fa18286 | 93 | return (caa_cycles_t) mftb(); |
9a9d403a TMQMF |
94 | } |
95 | #else | |
3fa18286 | 96 | static inline caa_cycles_t caa_get_cycles(void) |
9a9d403a TMQMF |
97 | { |
98 | unsigned long h, l; | |
6d0ce021 PM |
99 | |
100 | for (;;) { | |
101 | h = mftbu(); | |
5481ddb3 | 102 | cmm_barrier(); |
6d0ce021 | 103 | l = mftbl(); |
5481ddb3 | 104 | cmm_barrier(); |
6d0ce021 | 105 | if (mftbu() == h) |
3fa18286 | 106 | return (((caa_cycles_t) h) << 32) + l; |
6d0ce021 PM |
107 | } |
108 | } | |
9a9d403a | 109 | #endif |
121a5d44 | 110 | |
1b2c84f9 | 111 | /* |
84f4ccb4 MD |
112 | * On Linux, define the membarrier system call number if not yet available in |
113 | * the system headers. | |
1b2c84f9 | 114 | */ |
84f4ccb4 | 115 | #if (defined(__linux__) && !defined(__NR_membarrier)) |
1b2c84f9 MD |
116 | #define __NR_membarrier 365 |
117 | #endif | |
118 | ||
67ecffc0 | 119 | #ifdef __cplusplus |
36bc70a8 MD |
120 | } |
121 | #endif | |
122 | ||
1b9119f8 | 123 | #include <urcu/arch/generic.h> |
e4d1eb09 | 124 | |
ec4e58a3 | 125 | #endif /* _URCU_ARCH_PPC_H */ |