X-Git-Url: https://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch_x86.h;h=e3171a24fa608d044de77ad8633e67e4adbbc69f;hp=b3f29625142490530b3a813186bb094b069abdb5;hb=c53cf27f54bfb914e874ddb82a54653b6ccee276;hpb=36bc70a84250927ba68d5096a0a9740aec157f9b

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index b3f2962..e3171a2 100644
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -29,11 +29,9 @@
 extern "C" {
 #endif 
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
 #define CACHE_LINE_SIZE	128
 
-#ifdef CONFIG_URCU_HAVE_FENCE
+#ifdef CONFIG_RCU_HAVE_FENCE
 #define mb()    asm volatile("mfence":::"memory")
 #define rmb()   asm volatile("lfence":::"memory")
 #define wmb()   asm volatile("sfence"::: "memory")
@@ -47,69 +45,7 @@ extern "C" {
 #define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_URCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void rep_nop(void)
-{
-	asm volatile("rep; nop" : : : "memory");
-}
-
-static inline void cpu_relax(void)
-{
-	rep_nop();
-}
-
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-#ifdef __PIC__
-/*
- * Cannot use cpuid because it clobbers the ebx register and clashes
- * with -fPIC :
- * error: PIC register 'ebx' clobbered in 'asm'
- */
-static inline void sync_core(void)
-{
-	mb();
-}
-#else
-static inline void sync_core(void)
-{
-	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
-}
-#endif
+#define cpu_relax()	asm volatile("rep; nop" : : : "memory");
 
 #define rdtscll(val)							  \
 	do {						  		  \
@@ -133,4 +69,6 @@ static inline cycles_t get_cycles(void)
 }
 #endif
 
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_X86_H */