X-Git-Url: https://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch_x86.h;h=56250565e8001a08155f568148e1201f63324782;hp=f137a16d841c48e3c663a645286137ffe2114a04;hb=4a2f213c83ca73f35073b1460d3df683f0b9043c;hpb=618c4ae180e1d9406bcad808cd0cb88addc992a1

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index f137a16..5625056 100644
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -5,7 +5,7 @@
  * arch_x86.h: trivial definitions for the x86 architecture.
  *
  * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
- * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public
@@ -25,11 +25,13 @@
 #include <urcu/compiler.h>
 #include <urcu/config.h>
 
-#define CONFIG_HAVE_MEM_COHERENCY
+#ifdef __cplusplus
+extern "C" {
+#endif 
 
 #define CACHE_LINE_SIZE	128
 
-#ifdef CONFIG_URCU_HAVE_FENCE
+#ifdef CONFIG_RCU_HAVE_FENCE
 #define mb()    asm volatile("mfence":::"memory")
 #define rmb()   asm volatile("lfence":::"memory")
 #define wmb()   asm volatile("sfence"::: "memory")
@@ -43,69 +45,7 @@
 #define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_URCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void rep_nop(void)
-{
-	asm volatile("rep; nop" : : : "memory");
-}
-
-static inline void cpu_relax(void)
-{
-	rep_nop();
-}
-
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-#ifdef __PIC__
-/*
- * Cannot use cpuid because it clobbers the ebx register and clashes
- * with -fPIC :
- * error: PIC register 'ebx' clobbered in 'asm'
- */
-static inline void sync_core(void)
-{
-	mb();
-}
-#else
-static inline void sync_core(void)
-{
-	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
-}
-#endif
+#define cpu_relax()	asm volatile("rep; nop" : : : "memory");
 
 #define rdtscll(val)							  \
 	do {						  		  \
@@ -125,4 +65,10 @@ static inline cycles_t get_cycles(void)
         return ret;
 }
 
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_X86_H */