X-Git-Url: https://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch_sparc64.h;h=dbbbb422834b0ad7afd25300a468d964f448781f;hp=6dcb90810f75874e35dc3f63db93b17d7a8bf027;hb=6982d6d71aeed16d2d929bd0ed221e8f444b706e;hpb=36bc70a84250927ba68d5096a0a9740aec157f9b

diff --git a/urcu/arch_sparc64.h b/urcu/arch_sparc64.h
index 6dcb908..dbbbb42 100644
--- a/urcu/arch_sparc64.h
+++ b/urcu/arch_sparc64.h
@@ -5,7 +5,7 @@
  * arch_sparc64.h: trivial definitions for the Sparc64 architecture.
  *
  * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
- * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public
@@ -29,14 +29,8 @@
 extern "C" {
 #endif 
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
 #define CACHE_LINE_SIZE	256
 
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
-#endif
-
 /*
  * Inspired from the Linux kernel. Workaround Spitfire bug #51.
  */
@@ -50,53 +44,6 @@ __asm__ __volatile__("ba,pt %%xcc, 1f\n\t"	\
 #define rmb()    membar_safe("#LoadLoad")
 #define wmb()    membar_safe("#StoreStore")
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_URCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
-	barrier();
-}
-
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-static inline void sync_core()
-{
-	mb();
-}
-
 typedef unsigned long long cycles_t;
 
 static inline cycles_t get_cycles (void)
@@ -108,4 +55,6 @@ static inline cycles_t get_cycles (void)
 }
 #endif
 
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_SPARC64_H */