X-Git-Url: https://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch_ppc.h;h=1e096dbb893eca6e0cca03aba5858c7cee44f5c6;hp=c1762ae2d8dd3385b793f2df95a248695f7593c7;hb=e4d1eb09301904b56cdf22e1d6042df4492d57cb;hpb=455b809af97338c959280aee24a36699c4a947b5

diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h
index c1762ae..1e096db 100644
--- a/urcu/arch_ppc.h
+++ b/urcu/arch_ppc.h
@@ -29,8 +29,6 @@
 extern "C" {
 #endif 
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
 /* Include size of POWER5+ L3 cache lines: 256 bytes */
 #define CACHE_LINE_SIZE	256
 
@@ -39,55 +37,11 @@ extern "C" {
 #endif
 
 #define mb()    asm volatile("sync":::"memory")
-#define rmb()   asm volatile("sync":::"memory")
-#define wmb()   asm volatile("sync"::: "memory")
-
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_RCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
-	barrier();
-}
 
 /*
  * Serialize core instruction execution. Also acts as a compiler barrier.
  */
-static inline void sync_core()
-{
-	asm volatile("isync" : : : "memory");
-}
+#define sync_core()	asm volatile("isync" : : : "memory")
 
 #define mftbl()						\
 	({ 						\
@@ -123,4 +77,6 @@ static inline cycles_t get_cycles (void)
 }
 #endif
 
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_PPC_H */