X-Git-Url: https://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch%2Fx86.h;h=ecc4b2d39b4133cb026fbe98be6cace2c5c3e223;hp=5853604932793fb5fe40b5244fc5b33042393437;hb=999991c6e4600c410181baea65bda9f406464872;hpb=e51500edbd9919cee53bc85cbb4b22cd4786fc42

diff --git a/urcu/arch/x86.h b/urcu/arch/x86.h
index 5853604..ecc4b2d 100644
--- a/urcu/arch/x86.h
+++ b/urcu/arch/x86.h
@@ -24,6 +24,7 @@
 
 #include <urcu/compiler.h>
 #include <urcu/config.h>
+#include <urcu/syscall-compat.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -55,12 +56,18 @@ extern "C" {
  * IDT WinChip supports weak store ordering, and the kernel may enable it
  * under our feet; cmm_smp_wmb() ceases to be a nop for these processors.
  */
+#if (CAA_BITS_PER_LONG == 32)
 #define cmm_mb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
-#define cmm_rmb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
-#define cmm_wmb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)"::: "memory")
+#define cmm_rmb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_wmb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
+#else
+#define cmm_mb()    __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
+#define cmm_rmb()    __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
+#define cmm_wmb()    __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
+#endif
 #endif
 
-#define caa_cpu_relax()	__asm__ __volatile__ ("rep; nop" : : : "memory");
+#define caa_cpu_relax()	__asm__ __volatile__ ("rep; nop" : : : "memory")
 
 #define rdtscll(val)							  \
 	do {						  		  \
@@ -80,6 +87,20 @@ static inline cycles_t caa_get_cycles(void)
         return ret;
 }
 
+/*
+ * Define the membarrier system call number if not yet available in the
+ * system headers.
+ */
+#if (CAA_BITS_PER_LONG == 32)
+#ifndef __NR_membarrier
+#define __NR_membarrier		375
+#endif
+#else
+#ifndef __NR_membarrier
+#define __NR_membarrier		324
+#endif
+#endif
+
 #ifdef __cplusplus 
 }
 #endif