X-Git-Url: https://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch%2Fx86.h;h=7af1ca524e091fb9f9aaa8b6c2d1d102d3abe270;hp=5853604932793fb5fe40b5244fc5b33042393437;hb=b33e85a89e3fab8e58c8932d3d22e802de8d3ab2;hpb=8496c88699ea71aea6a8a244f20df4fcd558ffba

diff --git a/urcu/arch/x86.h b/urcu/arch/x86.h
index 5853604..7af1ca5 100644
--- a/urcu/arch/x86.h
+++ b/urcu/arch/x86.h
@@ -55,9 +55,15 @@ extern "C" {
  * IDT WinChip supports weak store ordering, and the kernel may enable it
  * under our feet; cmm_smp_wmb() ceases to be a nop for these processors.
  */
+#if (CAA_BITS_PER_LONG == 32)
 #define cmm_mb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
-#define cmm_rmb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
-#define cmm_wmb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)"::: "memory")
+#define cmm_rmb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_wmb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
+#else
+#define cmm_mb()    __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
+#define cmm_rmb()    __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
+#define cmm_wmb()    __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
+#endif
 #endif
 
 #define caa_cpu_relax()	__asm__ __volatile__ ("rep; nop" : : : "memory");