X-Git-Url: https://git.liburcu.org/?p=urcu.git;a=blobdiff_plain;f=urcu%2Farch%2Fppc.h;h=8a96dd9deb50626efe6a9a8b75e6cbab7c0dc628;hp=2fcbf5660958a12d2ad6dd957838ed73da4f2bec;hb=999991c6e4600c410181baea65bda9f406464872;hpb=e62b2f86c5ec06ed41d33ed578e66fad426ff215

diff --git a/urcu/arch/ppc.h b/urcu/arch/ppc.h
index 2fcbf56..8a96dd9 100644
--- a/urcu/arch/ppc.h
+++ b/urcu/arch/ppc.h
@@ -24,6 +24,7 @@
 
 #include <urcu/compiler.h>
 #include <urcu/config.h>
+#include <urcu/syscall-compat.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -46,7 +47,7 @@ extern "C" {
  * order cacheable and non-cacheable memory operations separately---i.e.
  * not the latter against the former.
  */
-#define cmm_mb()         asm volatile("sync":::"memory")
+#define cmm_mb()         __asm__ __volatile__ ("sync":::"memory")
 
 /*
  * lwsync orders loads in cacheable memory with respect to other loads,
@@ -54,27 +55,30 @@ extern "C" {
  * Therefore, use it for barriers ordering accesses to cacheable memory
  * only.
  */
-#define cmm_smp_rmb()    asm volatile(LWSYNC_OPCODE:::"memory")
-#define cmm_smp_wmb()    asm volatile(LWSYNC_OPCODE:::"memory")
+#define cmm_smp_rmb()    __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
+#define cmm_smp_wmb()    __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
 
 #define mftbl()						\
+	__extension__					\
 	({ 						\
 		unsigned long rval;			\
-		asm volatile("mftbl %0" : "=r" (rval));	\
+		__asm__ __volatile__ ("mftbl %0" : "=r" (rval));	\
 		rval;					\
 	})
 
 #define mftbu()						\
+	__extension__					\
 	({						\
 		unsigned long rval;			\
-		asm volatile("mftbu %0" : "=r" (rval));	\
+		__asm__ __volatile__ ("mftbu %0" : "=r" (rval));	\
 		rval;					\
 	})
 
 #define mftb()						\
+	__extension__					\
 	({						\
 		unsigned long long rval;		\
-		asm volatile("mftb %0" : "=r" (rval));	\
+		__asm__ __volatile__ ("mftb %0" : "=r" (rval));		\
 		rval;					\
 	})