define sync_core for x86 PIC

[urcu.git] / urcu / arch_x86.h

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index b3f29625142490530b3a813186bb094b069abdb5..64cc026f9cd46343cb977dc7b076bf9a7d70a317 100644 (file)
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -29,11 +29,9 @@
 extern "C" {
 #endif 
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
 #define CACHE_LINE_SIZE        128
 
-#ifdef CONFIG_URCU_HAVE_FENCE
+#ifdef CONFIG_RCU_HAVE_FENCE
 #define mb()    asm volatile("mfence":::"memory")
 #define rmb()   asm volatile("lfence":::"memory")
 #define wmb()   asm volatile("sfence"::: "memory")
@@ -47,68 +45,20 @@ extern "C" {
 #define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()                mc()
- * #define rmb()       rmc()
- * #define wmb()       wmc()
- * #define mc()                arch_cache_flush()
- * #define rmc()       arch_cache_flush_read()
- * #define wmc()       arch_cache_flush_write()
- */
-
-#define mc()   barrier()
-#define rmc()  barrier()
-#define wmc()  barrier()
-
-#ifdef CONFIG_URCU_SMP
-#define smp_mb()       mb()
-#define smp_rmb()      rmb()
-#define smp_wmb()      wmb()
-#define smp_mc()       mc()
-#define smp_rmc()      rmc()
-#define smp_wmc()      wmc()
-#else
-#define smp_mb()       barrier()
-#define smp_rmb()      barrier()
-#define smp_wmb()      barrier()
-#define smp_mc()       barrier()
-#define smp_rmc()      barrier()
-#define smp_wmc()      barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void rep_nop(void)
-{
-       asm volatile("rep; nop" : : : "memory");
-}
-
-static inline void cpu_relax(void)
-{
-       rep_nop();
-}
+#define cpu_relax()    asm volatile("rep; nop" : : : "memory");
 
 /*
  * Serialize core instruction execution. Also acts as a compiler barrier.
+ * On PIC ebx cannot be clobbered
  */
 #ifdef __PIC__
-/*
- * Cannot use cpuid because it clobbers the ebx register and clashes
- * with -fPIC :
- * error: PIC register 'ebx' clobbered in 'asm'
- */
-static inline void sync_core(void)
-{
-       mb();
-}
-#else
-static inline void sync_core(void)
-{
+#define sync_core()                                                      \
+       asm volatile("push %%ebx; cpuid; pop %%ebx"                       \
+                    : : : "memory", "eax", "ecx", "edx");
+#endif
+#ifndef __PIC__
+#define sync_core()                                                      \
        asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
-}
 #endif
 
 #define rdtscll(val)                                                     \
@@ -133,4 +83,6 @@ static inline cycles_t get_cycles(void)
 }
 #endif
 
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_X86_H */