add urcu/arch_generic.h

[urcu.git] / urcu / arch_sparc64.h

diff --git a/urcu/arch_sparc64.h b/urcu/arch_sparc64.h
index 54c4c3c49315c91f6b7ca255346ceac808f1c0f6..4d08d555a31fe4fb1cbfe99d17b57924ce9a2f95 100644 (file)
--- a/urcu/arch_sparc64.h
+++ b/urcu/arch_sparc64.h
@@ -29,8 +29,6 @@
 extern "C" {
 #endif 
 
-#define CONFIG_HAVE_MEM_COHERENCY
-
 #define CACHE_LINE_SIZE        256
 
 #ifndef BITS_PER_LONG
@@ -50,53 +48,6 @@ __asm__ __volatile__("ba,pt %%xcc, 1f\n\t"   \
 #define rmb()    membar_safe("#LoadLoad")
 #define wmb()    membar_safe("#StoreStore")
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()                mc()
- * #define rmb()       rmc()
- * #define wmb()       wmc()
- * #define mc()                arch_cache_flush()
- * #define rmc()       arch_cache_flush_read()
- * #define wmc()       arch_cache_flush_write()
- */
-
-#define mc()   barrier()
-#define rmc()  barrier()
-#define wmc()  barrier()
-
-#ifdef CONFIG_RCU_SMP
-#define smp_mb()       mb()
-#define smp_rmb()      rmb()
-#define smp_wmb()      wmb()
-#define smp_mc()       mc()
-#define smp_rmc()      rmc()
-#define smp_wmc()      wmc()
-#else
-#define smp_mb()       barrier()
-#define smp_rmb()      barrier()
-#define smp_wmb()      barrier()
-#define smp_mc()       barrier()
-#define smp_rmc()      barrier()
-#define smp_wmc()      barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
-       barrier();
-}
-
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-static inline void sync_core()
-{
-       mb();
-}
-
 typedef unsigned long long cycles_t;
 
 static inline cycles_t get_cycles (void)
@@ -108,4 +59,6 @@ static inline cycles_t get_cycles (void)
 }
 #endif
 
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_SPARC64_H */