rculfqueue: LGPL-ize

[urcu.git] / urcu / arch_ppc.h

diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h
index aaf61d30f03e7749823f0aff154987a07398e071..7a217c837dfb1cba0aad10ee0495e4d9adddd6e6 100644 (file)
--- a/urcu/arch_ppc.h
+++ b/urcu/arch_ppc.h
@@ -5,13 +5,13 @@
  * arch_ppc.h: trivial definitions for the powerpc architecture.
  *
  * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
- * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public
  * License as published by the Free Software Foundation; either
  * version 2.1 of the License, or (at your option) any later version.
-*
+ *
  * This library is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
@@ -23,71 +23,16 @@
  */
 
 #include <urcu/compiler.h>
-#include <urcu/arch_uatomic.h>
+#include <urcu/config.h>
 
-#define CONFIG_HAVE_FENCE 1
-#define CONFIG_HAVE_MEM_COHERENCY
+#ifdef __cplusplus
+extern "C" {
+#endif 
 
 /* Include size of POWER5+ L3 cache lines: 256 bytes */
 #define CACHE_LINE_SIZE        256
 
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG  (__SIZEOF_LONG__ * 8)
-#endif
-
 #define mb()    asm volatile("sync":::"memory")
-#define rmb()   asm volatile("sync":::"memory")
-#define wmb()   asm volatile("sync"::: "memory")
-
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()                mc()
- * #define rmb()       rmc()
- * #define wmb()       wmc()
- * #define mc()                arch_cache_flush()
- * #define rmc()       arch_cache_flush_read()
- * #define wmc()       arch_cache_flush_write()
- */
-
-#define mc()   barrier()
-#define rmc()  barrier()
-#define wmc()  barrier()
-
-/* Assume SMP machine, given we don't have this information */
-#define CONFIG_SMP 1
-
-#ifdef CONFIG_SMP
-#define smp_mb()       mb()
-#define smp_rmb()      rmb()
-#define smp_wmb()      wmb()
-#define smp_mc()       mc()
-#define smp_rmc()      rmc()
-#define smp_wmc()      wmc()
-#else
-#define smp_mb()       barrier()
-#define smp_rmb()      barrier()
-#define smp_wmb()      barrier()
-#define smp_mc()       barrier()
-#define smp_rmc()      barrier()
-#define smp_wmc()      barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
-       barrier();
-}
-
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-static inline void sync_core()
-{
-       asm volatile("isync" : : : "memory");
-}
 
 #define mftbl()                                                \
        ({                                              \
@@ -119,4 +64,10 @@ static inline cycles_t get_cycles (void)
        }
 }
 
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_PPC_H */