define CACHE_LINE_SIZE in arch_*.h

[urcu.git] / tests / test_urcu_gc.c

diff --git a/tests/test_urcu_gc.c b/tests/test_urcu_gc.c
index 60f7816b36fe50fa7d2ecf5a6d12a0ea38b8a8d8..162fae0490e3748decc57d04dd53909b05ad91a2 100644 (file)
--- a/tests/test_urcu_gc.c
+++ b/tests/test_urcu_gc.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384