define CACHE_LINE_SIZE in arch_*.h

[urcu.git] / tests / test_urcu_defer.c

diff --git a/tests/test_urcu_defer.c b/tests/test_urcu_defer.c
index 1c6f742b13aa841b47f203c39fa633ecf3f6db61..08e3e60b404927ae9c76b275f8bf12e5f498dc9a 100644 (file)
--- a/tests/test_urcu_defer.c
+++ b/tests/test_urcu_defer.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384