define CACHE_LINE_SIZE in arch_*.h

[urcu.git] / tests / test_urcu.c

diff --git a/tests/test_urcu.c b/tests/test_urcu.c
index 8d090ebdd070ab0fb3e64c010d91675365d48861..3b838c147e2b8ca3ddf866c6218937ac5c8ba2bb 100644 (file)
--- a/tests/test_urcu.c
+++ b/tests/test_urcu.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384