define CACHE_LINE_SIZE in arch_*.h

[urcu.git] / tests / test_qsbr_timing.c

diff --git a/tests/test_qsbr_timing.c b/tests/test_qsbr_timing.c
index 3585f83470a9ed28120312dd3d4c5fb8e4293b62..bbe983e8da53efba99733c94deb59466157f72b6 100644 (file)
--- a/tests/test_qsbr_timing.c
+++ b/tests/test_qsbr_timing.c
@@ -32,9 +32,6 @@
 #include <sys/syscall.h>
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)