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add rcu_cmpxchg_pointer
[urcu.git]
/
arch_atomic_ppc.h
diff --git
a/arch_atomic_ppc.h
b/arch_atomic_ppc.h
index 231a57798598e3da844d6938a95d9502b402da86..d696e26d1eb508ebc4c01d539975775903c3de4c 100644
(file)
--- a/
arch_atomic_ppc.h
+++ b/
arch_atomic_ppc.h
@@
-36,6
+36,13
@@
#ifndef _INCLUDE_API_H
#ifndef _INCLUDE_API_H
+#define atomic_set(addr, v) \
+do { \
+ ACCESS_ONCE(*(addr)) = (v); \
+} while (0)
+
+#define atomic_read(addr) ACCESS_ONCE(*(addr))
+
/*
* Using a isync as second barrier for exchange to provide acquire semantic.
* According to atomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
/*
* Using a isync as second barrier for exchange to provide acquire semantic.
* According to atomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
@@
-46,7
+53,7
@@
/* xchg */
static __attribute__((always_inline))
/* xchg */
static __attribute__((always_inline))
-unsigned long _atomic_exchange(vo
latile vo
id *addr, unsigned long val, int len)
+unsigned long _atomic_exchange(void *addr, unsigned long val, int len)
{
switch (len) {
case 4:
{
switch (len) {
case 4:
@@
-96,7
+103,7
@@
unsigned long _atomic_exchange(volatile void *addr, unsigned long val, int len)
/* cmpxchg */
static __attribute__((always_inline))
/* cmpxchg */
static __attribute__((always_inline))
-unsigned long _atomic_cmpxchg(vo
latile vo
id *addr, unsigned long old,
+unsigned long _atomic_cmpxchg(void *addr, unsigned long old,
unsigned long _new, int len)
{
switch (len) {
unsigned long _new, int len)
{
switch (len) {
@@
-156,7
+163,7
@@
unsigned long _atomic_cmpxchg(volatile void *addr, unsigned long old,
/* atomic_add_return */
static __attribute__((always_inline))
/* atomic_add_return */
static __attribute__((always_inline))
-unsigned long _atomic_add_return(vo
latile vo
id *addr, unsigned long val,
+unsigned long _atomic_add_return(void *addr, unsigned long val,
int len)
{
switch (len) {
int len)
{
switch (len) {
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