Add extern "C" to support linking userspace RCU library with C++ applications
[urcu.git] / urcu / arch_x86.h
1 #ifndef _URCU_ARCH_X86_H
2 #define _URCU_ARCH_X86_H
3
4 /*
5 * arch_x86.h: trivial definitions for the x86 architecture.
6 *
7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24
25 #include <urcu/compiler.h>
26 #include <urcu/config.h>
27
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31
32 #define CONFIG_HAVE_MEM_COHERENCY
33
34 #define CACHE_LINE_SIZE 128
35
36 #ifdef CONFIG_URCU_HAVE_FENCE
37 #define mb() asm volatile("mfence":::"memory")
38 #define rmb() asm volatile("lfence":::"memory")
39 #define wmb() asm volatile("sfence"::: "memory")
40 #else
41 /*
42 * Some non-Intel clones support out of order store. wmb() ceases to be a
43 * nop for these.
44 */
45 #define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
46 #define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
47 #define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
48 #endif
49
50 /*
51 * Architectures without cache coherency need something like the following:
52 *
53 * #define mb() mc()
54 * #define rmb() rmc()
55 * #define wmb() wmc()
56 * #define mc() arch_cache_flush()
57 * #define rmc() arch_cache_flush_read()
58 * #define wmc() arch_cache_flush_write()
59 */
60
61 #define mc() barrier()
62 #define rmc() barrier()
63 #define wmc() barrier()
64
65 #ifdef CONFIG_URCU_SMP
66 #define smp_mb() mb()
67 #define smp_rmb() rmb()
68 #define smp_wmb() wmb()
69 #define smp_mc() mc()
70 #define smp_rmc() rmc()
71 #define smp_wmc() wmc()
72 #else
73 #define smp_mb() barrier()
74 #define smp_rmb() barrier()
75 #define smp_wmb() barrier()
76 #define smp_mc() barrier()
77 #define smp_rmc() barrier()
78 #define smp_wmc() barrier()
79 #endif
80
81 /* Nop everywhere except on alpha. */
82 #define smp_read_barrier_depends()
83
84 static inline void rep_nop(void)
85 {
86 asm volatile("rep; nop" : : : "memory");
87 }
88
89 static inline void cpu_relax(void)
90 {
91 rep_nop();
92 }
93
94 /*
95 * Serialize core instruction execution. Also acts as a compiler barrier.
96 */
97 #ifdef __PIC__
98 /*
99 * Cannot use cpuid because it clobbers the ebx register and clashes
100 * with -fPIC :
101 * error: PIC register 'ebx' clobbered in 'asm'
102 */
103 static inline void sync_core(void)
104 {
105 mb();
106 }
107 #else
108 static inline void sync_core(void)
109 {
110 asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
111 }
112 #endif
113
114 #define rdtscll(val) \
115 do { \
116 unsigned int __a, __d; \
117 asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
118 (val) = ((unsigned long long)__a) \
119 | (((unsigned long long)__d) << 32); \
120 } while(0)
121
122 typedef unsigned long long cycles_t;
123
124 static inline cycles_t get_cycles(void)
125 {
126 cycles_t ret = 0;
127
128 rdtscll(ret);
129 return ret;
130 }
131
132 #ifdef __cplusplus
133 }
134 #endif
135
136 #endif /* _URCU_ARCH_X86_H */
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