Add extern "C" to support linking userspace RCU library with C++ applications
[urcu.git] / urcu / arch_sparc64.h
1 #ifndef _URCU_ARCH_SPARC64_H
2 #define _URCU_ARCH_SPARC64_H
3
4 /*
5 * arch_sparc64.h: trivial definitions for the Sparc64 architecture.
6 *
7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24
25 #include <urcu/compiler.h>
26 #include <urcu/config.h>
27
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31
32 #define CONFIG_HAVE_MEM_COHERENCY
33
34 #define CACHE_LINE_SIZE 256
35
36 #ifndef BITS_PER_LONG
37 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
38 #endif
39
40 /*
41 * Inspired from the Linux kernel. Workaround Spitfire bug #51.
42 */
43 #define membar_safe(type) \
44 __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
45 "membar " type "\n" \
46 "1:\n" \
47 : : : "memory")
48
49 #define mb() membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
50 #define rmb() membar_safe("#LoadLoad")
51 #define wmb() membar_safe("#StoreStore")
52
53 /*
54 * Architectures without cache coherency need something like the following:
55 *
56 * #define mb() mc()
57 * #define rmb() rmc()
58 * #define wmb() wmc()
59 * #define mc() arch_cache_flush()
60 * #define rmc() arch_cache_flush_read()
61 * #define wmc() arch_cache_flush_write()
62 */
63
64 #define mc() barrier()
65 #define rmc() barrier()
66 #define wmc() barrier()
67
68 #ifdef CONFIG_URCU_SMP
69 #define smp_mb() mb()
70 #define smp_rmb() rmb()
71 #define smp_wmb() wmb()
72 #define smp_mc() mc()
73 #define smp_rmc() rmc()
74 #define smp_wmc() wmc()
75 #else
76 #define smp_mb() barrier()
77 #define smp_rmb() barrier()
78 #define smp_wmb() barrier()
79 #define smp_mc() barrier()
80 #define smp_rmc() barrier()
81 #define smp_wmc() barrier()
82 #endif
83
84 /* Nop everywhere except on alpha. */
85 #define smp_read_barrier_depends()
86
87 static inline void cpu_relax(void)
88 {
89 barrier();
90 }
91
92 /*
93 * Serialize core instruction execution. Also acts as a compiler barrier.
94 */
95 static inline void sync_core()
96 {
97 mb();
98 }
99
100 typedef unsigned long long cycles_t;
101
102 static inline cycles_t get_cycles (void)
103 {
104 return 0; /* unimplemented */
105 }
106
107 #ifdef __cplusplus
108 }
109 #endif
110
111 #endif /* _URCU_ARCH_SPARC64_H */
This page took 0.042428 seconds and 4 git commands to generate.