0bef952ccd20095714bcb96839464a7fdf8681ff
[urcu.git] / urcu / arch / ppc.h
1 #ifndef _URCU_ARCH_PPC_H
2 #define _URCU_ARCH_PPC_H
3
4 /*
5 * arch_ppc.h: trivial definitions for the powerpc architecture.
6 *
7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24
25 #include <urcu/compiler.h>
26 #include <urcu/config.h>
27 #include <urcu/syscall-compat.h>
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 /* Include size of POWER5+ L3 cache lines: 256 bytes */
34 #define CAA_CACHE_LINE_SIZE 256
35
36 #ifdef __NO_LWSYNC__
37 #define LWSYNC_OPCODE "sync\n"
38 #else
39 #define LWSYNC_OPCODE "lwsync\n"
40 #endif
41
42 /*
43 * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not
44 * preserve ordering of cacheable vs. non-cacheable accesses, so it
45 * should not be used to order with respect to MMIO operations. An
46 * eieio+lwsync pair is also not enough for cmm_rmb, because it will
47 * order cacheable and non-cacheable memory operations separately---i.e.
48 * not the latter against the former.
49 */
50 #define cmm_mb() __asm__ __volatile__ ("sync":::"memory")
51
52 /*
53 * lwsync orders loads in cacheable memory with respect to other loads,
54 * and stores in cacheable memory with respect to other stores.
55 * Therefore, use it for barriers ordering accesses to cacheable memory
56 * only.
57 */
58 #define cmm_smp_rmb() __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
59 #define cmm_smp_wmb() __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
60
61 #define mftbl() \
62 __extension__ \
63 ({ \
64 unsigned long rval; \
65 __asm__ __volatile__ ("mftbl %0" : "=r" (rval)); \
66 rval; \
67 })
68
69 #define mftbu() \
70 __extension__ \
71 ({ \
72 unsigned long rval; \
73 __asm__ __volatile__ ("mftbu %0" : "=r" (rval)); \
74 rval; \
75 })
76
77 #define mftb() \
78 __extension__ \
79 ({ \
80 unsigned long long rval; \
81 __asm__ __volatile__ ("mftb %0" : "=r" (rval)); \
82 rval; \
83 })
84
85 #define HAS_CAA_GET_CYCLES
86
87 typedef unsigned long long cycles_t;
88
89 #ifdef __powerpc64__
90 static inline cycles_t caa_get_cycles(void)
91 {
92 return (cycles_t) mftb();
93 }
94 #else
95 static inline cycles_t caa_get_cycles(void)
96 {
97 unsigned long h, l;
98
99 for (;;) {
100 h = mftbu();
101 cmm_barrier();
102 l = mftbl();
103 cmm_barrier();
104 if (mftbu() == h)
105 return (((cycles_t) h) << 32) + l;
106 }
107 }
108 #endif
109
110 /*
111 * Define the membarrier system call number if not yet available in the
112 * system headers.
113 */
114 #ifndef __NR_membarrier
115 #define __NR_membarrier 365
116 #endif
117
118 #ifdef __cplusplus
119 }
120 #endif
121
122 #include <urcu/arch/generic.h>
123
124 #endif /* _URCU_ARCH_PPC_H */
This page took 0.042362 seconds and 4 git commands to generate.