aac8ca1384b63f4ce321680cffbcaca661a0f16c
[urcu.git] / include / urcu / arch / x86.h
1 #ifndef _URCU_ARCH_X86_H
2 #define _URCU_ARCH_X86_H
3
4 /*
5 * arch_x86.h: trivial definitions for the x86 architecture.
6 *
7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 */
24
25 #include <urcu/compiler.h>
26 #include <urcu/config.h>
27 #include <urcu/syscall-compat.h>
28 #include <stdint.h>
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34 #define CAA_CACHE_LINE_SIZE 128
35
36 #ifdef CONFIG_RCU_HAVE_FENCE
37 #define cmm_mb() __asm__ __volatile__ ("mfence":::"memory")
38
39 /*
40 * Define cmm_rmb/cmm_wmb to "strict" barriers that may be needed when
41 * using SSE or working with I/O areas. cmm_smp_rmb/cmm_smp_wmb are
42 * only compiler barriers, which is enough for general use.
43 */
44 #define cmm_rmb() __asm__ __volatile__ ("lfence":::"memory")
45 #define cmm_wmb() __asm__ __volatile__ ("sfence"::: "memory")
46 #define cmm_smp_rmb() cmm_barrier()
47 #define cmm_smp_wmb() cmm_barrier()
48 #else
49 /*
50 * We leave smp_rmb/smp_wmb as full barriers for processors that do not have
51 * fence instructions.
52 *
53 * An empty cmm_smp_rmb() may not be enough on old PentiumPro multiprocessor
54 * systems, due to an erratum. The Linux kernel says that "Even distro
55 * kernels should think twice before enabling this", but for now let's
56 * be conservative and leave the full barrier on 32-bit processors. Also,
57 * IDT WinChip supports weak store ordering, and the kernel may enable it
58 * under our feet; cmm_smp_wmb() ceases to be a nop for these processors.
59 */
60 #if (CAA_BITS_PER_LONG == 32)
61 #define cmm_mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
62 #define cmm_rmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
63 #define cmm_wmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
64 #else
65 #define cmm_mb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
66 #define cmm_rmb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
67 #define cmm_wmb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
68 #endif
69 #endif
70
71 #define caa_cpu_relax() __asm__ __volatile__ ("rep; nop" : : : "memory")
72
73 #define HAS_CAA_GET_CYCLES
74
75 #define rdtscll(val) \
76 do { \
77 unsigned int __a, __d; \
78 __asm__ __volatile__ ("rdtsc" : "=a" (__a), "=d" (__d)); \
79 (val) = ((unsigned long long)__a) \
80 | (((unsigned long long)__d) << 32); \
81 } while(0)
82
83 typedef uint64_t caa_cycles_t;
84
85 static inline caa_cycles_t caa_get_cycles(void)
86 {
87 caa_cycles_t ret = 0;
88
89 rdtscll(ret);
90 return ret;
91 }
92
93 /*
94 * On Linux, define the membarrier system call number if not yet available in
95 * the system headers.
96 */
97 #if (defined(__linux__) && !defined(__NR_membarrier))
98 #if (CAA_BITS_PER_LONG == 32)
99 #define __NR_membarrier 375
100 #else
101 #define __NR_membarrier 324
102 #endif
103 #endif
104
105 #ifdef __cplusplus
106 }
107 #endif
108
109 #include <urcu/arch/generic.h>
110
111 #endif /* _URCU_ARCH_X86_H */
This page took 0.043568 seconds and 3 git commands to generate.