[urcu.git] / urcu / arch_x86.h

#ifndef _URCU_ARCH_X86_H
#define _URCU_ARCH_X86_H

/*
 * arch_x86.h: trivial definitions for the x86 architecture.
 *
 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
*
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 */

#include <urcu/compiler.h>
#include <urcu/config.h>

#ifdef __cplusplus
extern "C" {
#endif 

#define CACHE_LINE_SIZE	128

#ifdef CONFIG_RCU_HAVE_FENCE
#define mb()    asm volatile("mfence":::"memory")
#define rmb()   asm volatile("lfence":::"memory")
#define wmb()   asm volatile("sfence"::: "memory")
#else
/*
 * Some non-Intel clones support out of order store. wmb() ceases to be a
 * nop for these.
 */
#define mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
#define rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
#define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
#endif

#define cpu_relax()	asm volatile("rep; nop" : : : "memory");

/*
 * Serialize core instruction execution. Also acts as a compiler barrier.
 * On PIC ebx cannot be clobbered
 */
#ifdef __PIC__
#define sync_core()							  \
	asm volatile("push %%ebx; cpuid; pop %%ebx"			  \
		     : : : "memory", "eax", "ecx", "edx");
#endif
#ifndef __PIC__
#define sync_core()							  \
	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
#endif

#define rdtscll(val)							  \
	do {						  		  \
	     unsigned int __a, __d;					  \
	     asm volatile("rdtsc" : "=a" (__a), "=d" (__d));		  \
	     (val) = ((unsigned long long)__a)				  \
			| (((unsigned long long)__d) << 32);		  \
	} while(0)

typedef unsigned long long cycles_t;

static inline cycles_t get_cycles(void)
{
        cycles_t ret = 0;

        rdtscll(ret);
        return ret;
}

#ifdef __cplusplus 
}
#endif

#include <urcu/arch_generic.h>

#endif /* _URCU_ARCH_X86_H */
Commit	Line	Data
	1	#ifndef _URCU_ARCH_X86_H
	2	#define _URCU_ARCH_X86_H
	3
	4	/*
	5	* arch_x86.h: trivial definitions for the x86 architecture.
	6	*
	7	* Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
	8	* Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
	9	*
	10	* This library is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU Lesser General Public
	12	* License as published by the Free Software Foundation; either
	13	* version 2.1 of the License, or (at your option) any later version.
	14	*
	15	* This library is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* Lesser General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU Lesser General Public
	21	* License along with this library; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
	23	*/
	24
	25	#include <urcu/compiler.h>
	26	#include <urcu/config.h>
	27
	28	#ifdef __cplusplus
	29	extern "C" {
	30	#endif
	31
	32	#define CACHE_LINE_SIZE 128
	33
	34	#ifdef CONFIG_RCU_HAVE_FENCE
	35	#define mb() asm volatile("mfence":::"memory")
	36	#define rmb() asm volatile("lfence":::"memory")
	37	#define wmb() asm volatile("sfence"::: "memory")
	38	#else
	39	/*
	40	* Some non-Intel clones support out of order store. wmb() ceases to be a
	41	* nop for these.
	42	*/
	43	#define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
	44	#define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
	45	#define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
	46	#endif
	47
	48	#define cpu_relax() asm volatile("rep; nop" : : : "memory");
	49
	50	/*
	51	* Serialize core instruction execution. Also acts as a compiler barrier.
	52	* On PIC ebx cannot be clobbered
	53	*/
	54	#ifdef __PIC__
	55	#define sync_core() \
	56	asm volatile("push %%ebx; cpuid; pop %%ebx" \
	57	: : : "memory", "eax", "ecx", "edx");
	58	#endif
	59	#ifndef __PIC__
	60	#define sync_core() \
	61	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
	62	#endif
	63
	64	#define rdtscll(val) \
	65	do { \
	66	unsigned int __a, __d; \
	67	asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
	68	(val) = ((unsigned long long)__a) \
	69	\| (((unsigned long long)__d) << 32); \
	70	} while(0)
	71
	72	typedef unsigned long long cycles_t;
	73
	74	static inline cycles_t get_cycles(void)
	75	{
	76	cycles_t ret = 0;
	77
	78	rdtscll(ret);
	79	return ret;
	80	}
	81
	82	#ifdef __cplusplus
	83	}
	84	#endif
	85
	86	#include <urcu/arch_generic.h>
	87
	88	#endif /* _URCU_ARCH_X86_H */