[urcu.git] / arch_atomic_x86.h

#ifndef _ARCH_ATOMIC_X86_H
#define _ARCH_ATOMIC_X86_H

/* 
 * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
 * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
 * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
 * Copyright (c) 2009      Mathieu Desnoyers
 *
 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
 * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
 *
 * Permission is hereby granted to use or copy this program
 * for any purpose,  provided the above notices are retained on all copies.
 * Permission to modify the code and to distribute modified code is granted,
 * provided the above notices are retained, and a notice that the code was
 * modified is included with the above copyright notice.
 *
 * Code inspired from libatomic_ops-1.2, inherited in part from the
 * Boehm-Demers-Weiser conservative garbage collector.
 */

#ifndef BITS_PER_LONG
#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
#endif

#ifndef _INCLUDE_API_H

/*
 * Using a isync as second barrier for exchange to provide acquire semantic.
 * According to atomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
 * explicit that this also has acquire semantics."
 * Derived from AO_compare_and_swap() and AO_test_and_set_full().
 */

static __attribute__((always_inline))
unsigned int atomic_exchange_32(volatile unsigned int *addr, unsigned int val)
{
	unsigned int result;

	__asm__ __volatile__(
		/* Note: the "xchg" instruction does not need a "lock" prefix */
		"xchgl %0, %1"
			: "=&r"(result), "=m"(*addr)
			: "0" (val), "m"(*addr)
			: "memory");

	return result;
}

#if (BITS_PER_LONG == 64)

static __attribute__((always_inline))
unsigned long atomic_exchange_64(volatile unsigned long *addr,
				 unsigned long val)
{
	unsigned long result;

	__asm__ __volatile__(
		/* Note: the "xchg" instruction does not need a "lock" prefix */
		"xchgq %0, %1"
			: "=&r"(result), "=m"(*addr)
			: "0" (val), "m"(*addr)
			: "memory");

	return result;
}

#endif

static __attribute__((always_inline))
unsigned long _atomic_exchange(volatile void *addr, unsigned long val, int len)
{
	switch (len) {
	case 4:	return atomic_exchange_32(addr, val);
#if (BITS_PER_LONG == 64)
	case 8:	return atomic_exchange_64(addr, val);
#endif
	}
	/* generate an illegal instruction. Cannot catch this with linker tricks
	 * when optimizations are disabled. */
	__asm__ __volatile__("ud2");
	return 0;
}

#define xchg(addr, v)							    \
	((__typeof__(*(addr))) _atomic_exchange((addr), (unsigned long)(v), \
						sizeof(*(addr))))

#endif /* #ifndef _INCLUDE_API_H */

#endif /* ARCH_ATOMIC_X86_H */
Commit	Line	Data
	1	#ifndef _ARCH_ATOMIC_X86_H
	2	#define _ARCH_ATOMIC_X86_H
	3
	4	/*
	5	* Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
	6	* Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
	7	* Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
	8	* Copyright (c) 2009 Mathieu Desnoyers
	9	*
	10	* THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
	11	* OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
	12	*
	13	* Permission is hereby granted to use or copy this program
	14	* for any purpose, provided the above notices are retained on all copies.
	15	* Permission to modify the code and to distribute modified code is granted,
	16	* provided the above notices are retained, and a notice that the code was
	17	* modified is included with the above copyright notice.
	18	*
	19	* Code inspired from libatomic_ops-1.2, inherited in part from the
	20	* Boehm-Demers-Weiser conservative garbage collector.
	21	*/
	22
	23	#ifndef BITS_PER_LONG
	24	#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
	25	#endif
	26
	27	#ifndef _INCLUDE_API_H
	28
	29	/*
	30	* Using a isync as second barrier for exchange to provide acquire semantic.
	31	* According to atomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
	32	* explicit that this also has acquire semantics."
	33	* Derived from AO_compare_and_swap() and AO_test_and_set_full().
	34	*/
	35
	36	static __attribute__((always_inline))
	37	unsigned int atomic_exchange_32(volatile unsigned int *addr, unsigned int val)
	38	{
	39	unsigned int result;
	40
	41	__asm__ __volatile__(
	42	/* Note: the "xchg" instruction does not need a "lock" prefix */
	43	"xchgl %0, %1"
	44	: "=&r"(result), "=m"(*addr)
	45	: "0" (val), "m"(*addr)
	46	: "memory");
	47
	48	return result;
	49	}
	50
	51	#if (BITS_PER_LONG == 64)
	52
	53	static __attribute__((always_inline))
	54	unsigned long atomic_exchange_64(volatile unsigned long *addr,
	55	unsigned long val)
	56	{
	57	unsigned long result;
	58
	59	__asm__ __volatile__(
	60	/* Note: the "xchg" instruction does not need a "lock" prefix */
	61	"xchgq %0, %1"
	62	: "=&r"(result), "=m"(*addr)
	63	: "0" (val), "m"(*addr)
	64	: "memory");
	65
	66	return result;
	67	}
	68
	69	#endif
	70
	71	static __attribute__((always_inline))
	72	unsigned long _atomic_exchange(volatile void *addr, unsigned long val, int len)
	73	{
	74	switch (len) {
	75	case 4: return atomic_exchange_32(addr, val);
	76	#if (BITS_PER_LONG == 64)
	77	case 8: return atomic_exchange_64(addr, val);
	78	#endif
	79	}
	80	/* generate an illegal instruction. Cannot catch this with linker tricks
	81	* when optimizations are disabled. */
	82	__asm__ __volatile__("ud2");
	83	return 0;
	84	}
	85
	86	#define xchg(addr, v) \
	87	((__typeof__(*(addr))) _atomic_exchange((addr), (unsigned long)(v), \
	88	sizeof(*(addr))))
	89
	90	#endif /* #ifndef _INCLUDE_API_H */
	91
	92	#endif /* ARCH_ATOMIC_X86_H */