Implementation of xchg primitives derived from MIT license
[urcu.git] / arch_atomic_ppc.h
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1#ifndef _ARCH_ATOMIC_PPC_H
2#define _ARCH_ATOMIC_PPC_H
3
4/*
5 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
6 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
7 * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
8 * Copyright (c) 2009 Mathieu Desnoyers
9 *
10 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
11 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
12 *
13 * Permission is hereby granted to use or copy this program
14 * for any purpose, provided the above notices are retained on all copies.
15 * Permission to modify the code and to distribute modified code is granted,
16 * provided the above notices are retained, and a notice that the code was
17 * modified is included with the above copyright notice.
18 *
19 * Code inspired from libatomic_ops-1.2, inherited in part from the
20 * Boehm-Demers-Weiser conservative garbage collector.
21 */
22
23#ifndef BITS_PER_LONG
24#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
25#endif
26
27#define ILLEGAL_INSTR .long 0xd00d00
28
29#ifndef _INCLUDE_API_H
30
31/*
32 * Using a isync as second barrier for exchange to provide acquire semantic.
33 * According to atomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
34 * explicit that this also has acquire semantics."
35 * Derived from AO_compare_and_swap(), but removed the comparison.
36 */
37
38static __attribute__((always_inline))
39unsigned int atomic_exchange_32(volatile unsigned int *addr, unsigned int val)
40{
41 unsigned int result;
42
43 __asm__ __volatile__(
44 "lwsync\n"
45 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
46 "stwcx. %2,0,%1\n" /* else store conditional */
47 "bne- 1b\n" /* retry if lost reservation */
48 "isync\n"
49 : "=&r"(result),
50 : "r"(addr), "r"(val)
51 : "memory", "cc");
52
53 return result;
54}
55
56#if (BITS_PER_LONG == 64)
57
58static __attribute__((always_inline))
59unsigned long atomic_exchange_64(volatile unsigned long *addr,
60 unsigned long val)
61{
62 unsigned long result;
63
64 __asm__ __volatile__(
65 "lwsync\n"
66 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
67 "stdcx. %2,0,%1\n" /* else store conditional */
68 "bne- 1b\n" /* retry if lost reservation */
69 "isync\n"
70 : "=&r"(result),
71 : "r"(addr), "r"(val)
72 : "memory", "cc");
73
74 return result;
75}
76
77#endif
78
79static __attribute__((always_inline))
80unsigned long _atomic_exchange(volatile void *addr, unsigned long val, int len)
81{
82 switch (len) {
83 case 4: return atomic_exchange_32(addr, val);
84#if (BITS_PER_LONG == 64)
85 case 8: return atomic_exchange_64(addr, val);
86#endif
87 }
88 /* generate an illegal instruction. Cannot catch this with linker tricks
89 * when optimizations are disabled. */
90 __asm__ __volatile__(ILLEGAL_INSTR);
91 return 0;
92}
93
94#define xchg(addr, v) (__typeof__(*(addr)) _atomic_exchange((addr), (v), \
95 sizeof(*(addr))))
96
97#endif /* #ifndef _INCLUDE_API_H */
98
99#endif /* ARCH_ATOMIC_PPC_H */
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