X-Git-Url: https://git.liburcu.org/?a=blobdiff_plain;f=urcu%2Farch_x86.h;h=c4674de0d35adfbe3eaa19560ba3a4750583fecb;hb=e4d1eb09301904b56cdf22e1d6042df4492d57cb;hp=806878e26791132b1813c1ca25197efee59b06ce;hpb=7d413817f09b2d17b1a79ea012590609ffab5eb6;p=urcu.git

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index 806878e..c4674de 100644
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -23,19 +23,15 @@
  */
 
 #include <urcu/compiler.h>
-#include "config.h"
+#include <urcu/config.h>
 
-/* Assume P4 or newer */
-#define CONFIG_HAVE_FENCE 1
-#define CONFIG_HAVE_MEM_COHERENCY
+#ifdef __cplusplus
+extern "C" {
+#endif 
 
 #define CACHE_LINE_SIZE	128
 
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG	(__SIZEOF_LONG__ * 8)
-#endif
-
-#ifdef CONFIG_HAVE_FENCE
+#ifdef CONFIG_RCU_HAVE_FENCE
 #define mb()    asm volatile("mfence":::"memory")
 #define rmb()   asm volatile("lfence":::"memory")
 #define wmb()   asm volatile("sfence"::: "memory")
@@ -49,68 +45,16 @@
 #define wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void rep_nop(void)
-{
-	asm volatile("rep; nop" : : : "memory");
-}
-
-static inline void cpu_relax(void)
-{
-	rep_nop();
-}
+#define cpu_relax()	asm volatile("rep; nop" : : : "memory");
 
 /*
  * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-#ifdef __PIC__
-/*
- * Cannot use cpuid because it clobbers the ebx register and clashes
- * with -fPIC :
+ * Cannot use cpuid on PIC because it clobbers the ebx register;
  * error: PIC register 'ebx' clobbered in 'asm'
  */
-static inline void sync_core(void)
-{
-	mb();
-}
-#else
-static inline void sync_core(void)
-{
+#ifndef __PIC__
+#define sync_core()							  \
 	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
-}
 #endif
 
 #define rdtscll(val)							  \
@@ -131,4 +75,10 @@ static inline cycles_t get_cycles(void)
         return ret;
 }
 
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_X86_H */