X-Git-Url: https://git.liburcu.org/?a=blobdiff_plain;f=urcu%2Farch_sparc64.h;h=4d08d555a31fe4fb1cbfe99d17b57924ce9a2f95;hb=8760d94e0ef6d52260765a9246aaac073613055e;hp=a260e3a39abb29b94124cf838dd137a9be234849;hpb=58de5a4bc81e0b64f4fbd46973b5c8b0cd06cda6;p=urcu.git

diff --git a/urcu/arch_sparc64.h b/urcu/arch_sparc64.h
index a260e3a..4d08d55 100644
--- a/urcu/arch_sparc64.h
+++ b/urcu/arch_sparc64.h
@@ -25,7 +25,9 @@
 #include <urcu/compiler.h>
 #include <urcu/config.h>
 
-#define CONFIG_HAVE_MEM_COHERENCY
+#ifdef __cplusplus
+extern "C" {
+#endif 
 
 #define CACHE_LINE_SIZE	256
 
@@ -46,53 +48,6 @@ __asm__ __volatile__("ba,pt %%xcc, 1f\n\t"	\
 #define rmb()    membar_safe("#LoadLoad")
 #define wmb()    membar_safe("#StoreStore")
 
-/*
- * Architectures without cache coherency need something like the following:
- *
- * #define mb()		mc()
- * #define rmb()	rmc()
- * #define wmb()	wmc()
- * #define mc()		arch_cache_flush()
- * #define rmc()	arch_cache_flush_read()
- * #define wmc()	arch_cache_flush_write()
- */
-
-#define mc()	barrier()
-#define rmc()	barrier()
-#define wmc()	barrier()
-
-#ifdef CONFIG_URCU_SMP
-#define smp_mb()	mb()
-#define smp_rmb()	rmb()
-#define smp_wmb()	wmb()
-#define smp_mc()	mc()
-#define smp_rmc()	rmc()
-#define smp_wmc()	wmc()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_mc()	barrier()
-#define smp_rmc()	barrier()
-#define smp_wmc()	barrier()
-#endif
-
-/* Nop everywhere except on alpha. */
-#define smp_read_barrier_depends()
-
-static inline void cpu_relax(void)
-{
-	barrier();
-}
-
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-static inline void sync_core()
-{
-	mb();
-}
-
 typedef unsigned long long cycles_t;
 
 static inline cycles_t get_cycles (void)
@@ -100,4 +55,10 @@ static inline cycles_t get_cycles (void)
 	return 0;	/* unimplemented */
 }
 
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/arch_generic.h>
+
 #endif /* _URCU_ARCH_SPARC64_H */