X-Git-Url: https://git.liburcu.org/?a=blobdiff_plain;f=urcu%2Farch_ppc.h;h=b0f503001eef91fc3faa85c78e938f78f8440a20;hb=85b577030e0dd244ed2d42aa5196a088e1e64dbb;hp=1e096dbb893eca6e0cca03aba5858c7cee44f5c6;hpb=e4d1eb09301904b56cdf22e1d6042df4492d57cb;p=urcu.git diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h index 1e096db..b0f5030 100644 --- a/urcu/arch_ppc.h +++ b/urcu/arch_ppc.h @@ -5,13 +5,13 @@ * arch_ppc.h: trivial definitions for the powerpc architecture. * * Copyright (c) 2009 Paul E. McKenney, IBM Corporation. - * Copyright (c) 2009 Mathieu Desnoyers + * Copyright (c) 2009 Mathieu Desnoyers * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. -* + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU @@ -30,18 +30,9 @@ extern "C" { #endif /* Include size of POWER5+ L3 cache lines: 256 bytes */ -#define CACHE_LINE_SIZE 256 - -#ifndef BITS_PER_LONG -#define BITS_PER_LONG (__SIZEOF_LONG__ * 8) -#endif +#define CAA_CACHE_LINE_SIZE 256 -#define mb() asm volatile("sync":::"memory") - -/* - * Serialize core instruction execution. Also acts as a compiler barrier. - */ -#define sync_core() asm volatile("isync" : : : "memory") +#define cmm_mb() asm volatile("sync":::"memory") #define mftbl() \ ({ \ @@ -59,15 +50,15 @@ extern "C" { typedef unsigned long long cycles_t; -static inline cycles_t get_cycles (void) +static inline cycles_t caa_get_cycles (void) { long h, l; for (;;) { h = mftbu(); - barrier(); + cmm_barrier(); l = mftbl(); - barrier(); + cmm_barrier(); if (mftbu() == h) return (((cycles_t) h) << 32) + l; }