X-Git-Url: https://git.liburcu.org/?a=blobdiff_plain;f=urcu%2Farch_ppc.h;h=1e096dbb893eca6e0cca03aba5858c7cee44f5c6;hb=8760d94e0ef6d52260765a9246aaac073613055e;hp=12b018eef7d90276524d56e8606ab3786e615a0b;hpb=49617de1d80d771ac9a1d45b1710b16fac65e0aa;p=urcu.git diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h index 12b018e..1e096db 100644 --- a/urcu/arch_ppc.h +++ b/urcu/arch_ppc.h @@ -25,7 +25,9 @@ #include #include -#define CONFIG_HAVE_MEM_COHERENCY +#ifdef __cplusplus +extern "C" { +#endif /* Include size of POWER5+ L3 cache lines: 256 bytes */ #define CACHE_LINE_SIZE 256 @@ -35,55 +37,11 @@ #endif #define mb() asm volatile("sync":::"memory") -#define rmb() asm volatile("sync":::"memory") -#define wmb() asm volatile("sync"::: "memory") - -/* - * Architectures without cache coherency need something like the following: - * - * #define mb() mc() - * #define rmb() rmc() - * #define wmb() wmc() - * #define mc() arch_cache_flush() - * #define rmc() arch_cache_flush_read() - * #define wmc() arch_cache_flush_write() - */ - -#define mc() barrier() -#define rmc() barrier() -#define wmc() barrier() - -#ifdef CONFIG_URCU_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_mc() mc() -#define smp_rmc() rmc() -#define smp_wmc() wmc() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_mc() barrier() -#define smp_rmc() barrier() -#define smp_wmc() barrier() -#endif - -/* Nop everywhere except on alpha. */ -#define smp_read_barrier_depends() - -static inline void cpu_relax(void) -{ - barrier(); -} /* * Serialize core instruction execution. Also acts as a compiler barrier. */ -static inline void sync_core() -{ - asm volatile("isync" : : : "memory"); -} +#define sync_core() asm volatile("isync" : : : "memory") #define mftbl() \ ({ \ @@ -115,4 +73,10 @@ static inline cycles_t get_cycles (void) } } +#ifdef __cplusplus +} +#endif + +#include + #endif /* _URCU_ARCH_PPC_H */