X-Git-Url: https://git.liburcu.org/?a=blobdiff_plain;f=urcu%2Farch%2Fppc.h;h=048b217392cc7cd471647625ca1dd128e6627e00;hb=8c35d699cf442f91fbba3c99beaa41a083ef7bff;hp=d7317bb327c72afa48f087f50251cbe311a2ff62;hpb=9d2614f07691a813a3c560a6c0bcd0a7be854ed5;p=urcu.git

diff --git a/urcu/arch/ppc.h b/urcu/arch/ppc.h
index d7317bb..048b217 100644
--- a/urcu/arch/ppc.h
+++ b/urcu/arch/ppc.h
@@ -32,7 +32,24 @@ extern "C" {
 /* Include size of POWER5+ L3 cache lines: 256 bytes */
 #define CAA_CACHE_LINE_SIZE	256
 
-#define cmm_mb()    asm volatile("sync":::"memory")
+/*
+ * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not
+ * preserve ordering of cacheable vs. non-cacheable accesses, so it
+ * should not be used to order with respect to MMIO operations.  An
+ * eieio+lwsync pair is also not enough for cmm_rmb, because it will
+ * order cacheable and non-cacheable memory operations separately---i.e.
+ * not the latter against the former.
+ */
+#define cmm_mb()         asm volatile("sync":::"memory")
+
+/*
+ * lwsync orders loads in cacheable memory with respect to other loads,
+ * and stores in cacheable memory with respect to other stores.
+ * Therefore, use it for barriers ordering accesses to cacheable memory
+ * only.
+ */
+#define cmm_smp_rmb()    asm volatile("lwsync":::"memory")
+#define cmm_smp_wmb()    asm volatile("lwsync":::"memory")
 
 #define mftbl()						\
 	({ 						\
@@ -48,11 +65,24 @@ extern "C" {
 		rval;					\
 	})
 
+#define mftb()						\
+	({						\
+		unsigned long long rval;		\
+		asm volatile("mftb %0" : "=r" (rval));	\
+		rval;					\
+	})
+
 typedef unsigned long long cycles_t;
 
-static inline cycles_t caa_get_cycles (void)
+#ifdef __powerpc64__
+static inline cycles_t caa_get_cycles(void)
 {
-	long h, l;
+	return (cycles_t) mftb();
+}
+#else
+static inline cycles_t caa_get_cycles(void)
+{
+	unsigned long h, l;
 
 	for (;;) {
 		h = mftbu();
@@ -63,6 +93,7 @@ static inline cycles_t caa_get_cycles (void)
 			return (((cycles_t) h) << 32) + l;
 	}
 }
+#endif
 
 #ifdef __cplusplus 
 }