/* Include size of POWER5+ L3 cache lines: 256 bytes */
#define CACHE_LINE_SIZE 256
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
-#endif
-
#define mb() asm volatile("sync":::"memory")
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-#define sync_core() asm volatile("isync" : : : "memory")
-
#define mftbl() \
({ \
unsigned long rval; \