*/
#include <urcu/compiler.h>
+#include <urcu/config.h>
-#define CONFIG_HAVE_FENCE 1
#define CONFIG_HAVE_MEM_COHERENCY
/* Include size of POWER5+ L3 cache lines: 256 bytes */
#define rmc() barrier()
#define wmc() barrier()
-/* Assume SMP machine, given we don't have this information */
-#define CONFIG_SMP 1
-
-#ifdef CONFIG_SMP
+#ifdef CONFIG_URCU_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()