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Fix int->long and keep a reader count of 1 in the global GP variable
[userspace-rcu.git]
/
urcu.h
diff --git
a/urcu.h
b/urcu.h
index bc86d435845d6da33255a63d7d5d2fbdecb4aa76..9e9fea2b96fafa5c4688a1b1bf696284587df25f 100644
(file)
--- a/
urcu.h
+++ b/
urcu.h
@@
-17,12
+17,15
@@
* Distributed under GPLv2
*/
* Distributed under GPLv2
*/
-#define __USE_GNU
#include <stdlib.h>
#include <stdlib.h>
+#include <pthread.h>
/* The "volatile" is due to gcc bugs */
#define barrier() __asm__ __volatile__("": : :"memory")
/* The "volatile" is due to gcc bugs */
#define barrier() __asm__ __volatile__("": : :"memory")
+#define likely(x) __builtin_expect(!!(x), 1)
+#define unlikely(x) __builtin_expect(!!(x), 0)
+
/* x86 32/64 specific */
#define mb() asm volatile("mfence":::"memory")
#define rmb() asm volatile("lfence":::"memory")
/* x86 32/64 specific */
#define mb() asm volatile("mfence":::"memory")
#define rmb() asm volatile("lfence":::"memory")
@@
-64,7
+67,13
@@
static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
: "memory");
break;
case 4:
: "memory");
break;
case 4:
- asm volatile("xchgl %0,%1"
+ asm volatile("xchgl %k0,%1"
+ : "=r" (x)
+ : "m" (*__xg(ptr)), "0" (x)
+ : "memory");
+ break;
+ case 8:
+ asm volatile("xchgq %0,%1"
: "=r" (x)
: "m" (*__xg(ptr)), "0" (x)
: "memory");
: "=r" (x)
: "m" (*__xg(ptr)), "0" (x)
: "memory");
@@
-153,21
+162,26
@@
static inline void debug_yield_init(void)
#endif
/*
#endif
/*
- *
Limiting the nesting level to 256 to keep instructions small in the read
- * f
ast-path
.
+ *
The trick here is that RCU_GP_CTR_BIT must be a multiple of 8 so we can use a
+ * f
ull 8-bits, 16-bits or 32-bits bitmask for the lower order bits
.
*/
*/
-#define RCU_GP_COUNT (1U << 0)
-#define RCU_GP_CTR_BIT (1U << 8)
+#define RCU_GP_COUNT (1UL << 0)
+/* Use the amount of bits equal to half of the architecture long size */
+#define RCU_GP_CTR_BIT (1UL << (sizeof(long) << 2))
#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
#define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
-/* Global quiescent period counter with low-order bits unused. */
-extern int urcu_gp_ctr;
+/*
+ * Global quiescent period counter with low-order bits unused.
+ * Using a int rather than a char to eliminate false register dependencies
+ * causing stalls on some architectures.
+ */
+extern long urcu_gp_ctr;
-extern
int
__thread urcu_active_readers;
+extern
long
__thread urcu_active_readers;
-static inline int rcu_old_gp_ongoing(
int
*value)
+static inline int rcu_old_gp_ongoing(
long
*value)
{
{
-
int
v;
+
long
v;
if (value == NULL)
return 0;
if (value == NULL)
return 0;
@@
-180,13
+194,13
@@
static inline int rcu_old_gp_ongoing(int *value)
static inline void rcu_read_lock(void)
{
static inline void rcu_read_lock(void)
{
-
int
tmp;
+
long
tmp;
debug_yield_read();
tmp = urcu_active_readers;
debug_yield_read();
debug_yield_read();
tmp = urcu_active_readers;
debug_yield_read();
- if (
!(tmp & RCU_GP_CTR_NEST_MASK
))
- urcu_active_readers = urcu_gp_ctr
+ RCU_GP_COUNT
;
+ if (
likely(!(tmp & RCU_GP_CTR_NEST_MASK)
))
+ urcu_active_readers = urcu_gp_ctr;
else
urcu_active_readers = tmp + RCU_GP_COUNT;
debug_yield_read();
else
urcu_active_readers = tmp + RCU_GP_COUNT;
debug_yield_read();
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