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Update email address from @polymtl.ca to @efficios.com
[userspace-rcu.git]
/
urcu
/
arch_ppc.h
diff --git
a/urcu/arch_ppc.h
b/urcu/arch_ppc.h
index 1e096dbb893eca6e0cca03aba5858c7cee44f5c6..8b3eb758f151bbbac1c9060787909fcfdd1de1ef 100644
(file)
--- a/
urcu/arch_ppc.h
+++ b/
urcu/arch_ppc.h
@@
-5,7
+5,7
@@
* arch_ppc.h: trivial definitions for the powerpc architecture.
*
* Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
* arch_ppc.h: trivial definitions for the powerpc architecture.
*
* Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
- * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@
polymtl.ca
>
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@
efficios.com
>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@
-32,17
+32,8
@@
extern "C" {
/* Include size of POWER5+ L3 cache lines: 256 bytes */
#define CACHE_LINE_SIZE 256
/* Include size of POWER5+ L3 cache lines: 256 bytes */
#define CACHE_LINE_SIZE 256
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
-#endif
-
#define mb() asm volatile("sync":::"memory")
#define mb() asm volatile("sync":::"memory")
-/*
- * Serialize core instruction execution. Also acts as a compiler barrier.
- */
-#define sync_core() asm volatile("isync" : : : "memory")
-
#define mftbl() \
({ \
unsigned long rval; \
#define mftbl() \
({ \
unsigned long rval; \
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