1 #ifndef _URCU_ARCH_UATOMIC_PPC_H
2 #define _URCU_ARCH_UATOMIC_PPC_H
5 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
6 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
7 * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
8 * Copyright (c) 2009 Mathieu Desnoyers
10 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
11 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
13 * Permission is hereby granted to use or copy this program
14 * for any purpose, provided the above notices are retained on all copies.
15 * Permission to modify the code and to distribute modified code is granted,
16 * provided the above notices are retained, and a notice that the code was
17 * modified is included with the above copyright notice.
19 * Code inspired from libuatomic_ops-1.2, inherited in part from the
20 * Boehm-Demers-Weiser conservative garbage collector.
23 #include <urcu/compiler.h>
24 #include <urcu/system.h>
30 #ifndef __SIZEOF_LONG__
32 #define __SIZEOF_LONG__ 8
34 #define __SIZEOF_LONG__ 4
39 #define LWSYNC_OPCODE "sync\n"
41 #define LWSYNC_OPCODE "lwsync\n"
45 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
48 #define ILLEGAL_INSTR ".long 0xd00d00"
51 * Using a isync as second barrier for exchange to provide acquire semantic.
52 * According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
53 * explicit that this also has acquire semantics."
54 * Derived from AO_compare_and_swap(), but removed the comparison.
59 static inline __attribute__((always_inline
))
60 unsigned long _uatomic_exchange(void *addr
, unsigned long val
, int len
)
69 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
70 "stwcx. %2,0,%1\n" /* else store conditional */
71 "bne- 1b\n" /* retry if lost reservation */
79 #if (BITS_PER_LONG == 64)
86 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
87 "stdcx. %2,0,%1\n" /* else store conditional */
88 "bne- 1b\n" /* retry if lost reservation */
98 /* generate an illegal instruction. Cannot catch this with linker tricks
99 * when optimizations are disabled. */
100 __asm__
__volatile__(ILLEGAL_INSTR
);
104 #define uatomic_xchg(addr, v) \
105 ((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
109 static inline __attribute__((always_inline
))
110 unsigned long _uatomic_cmpxchg(void *addr
, unsigned long old
,
111 unsigned long _new
, int len
)
116 unsigned int old_val
;
118 __asm__
__volatile__(
120 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
121 "cmpd %0,%3\n" /* if load is not equal to */
122 "bne 2f\n" /* old, fail */
123 "stwcx. %2,0,%1\n" /* else store conditional */
124 "bne- 1b\n" /* retry if lost reservation */
128 : "r"(addr
), "r"((unsigned int)_new
),
129 "r"((unsigned int)old
)
134 #if (BITS_PER_LONG == 64)
137 unsigned long old_val
;
139 __asm__
__volatile__(
141 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
142 "cmpd %0,%3\n" /* if load is not equal to */
143 "bne 2f\n" /* old, fail */
144 "stdcx. %2,0,%1\n" /* else store conditional */
145 "bne- 1b\n" /* retry if lost reservation */
149 : "r"(addr
), "r"((unsigned long)_new
),
150 "r"((unsigned long)old
)
157 /* generate an illegal instruction. Cannot catch this with linker tricks
158 * when optimizations are disabled. */
159 __asm__
__volatile__(ILLEGAL_INSTR
);
164 #define uatomic_cmpxchg(addr, old, _new) \
165 ((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
166 (unsigned long)(_new), \
169 /* uatomic_add_return */
171 static inline __attribute__((always_inline
))
172 unsigned long _uatomic_add_return(void *addr
, unsigned long val
,
180 __asm__
__volatile__(
182 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
183 "add %0,%2,%0\n" /* add val to value loaded */
184 "stwcx. %0,0,%1\n" /* store conditional */
185 "bne- 1b\n" /* retry if lost reservation */
188 : "r"(addr
), "r"(val
)
193 #if (BITS_PER_LONG == 64)
196 unsigned long result
;
198 __asm__
__volatile__(
200 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
201 "add %0,%2,%0\n" /* add val to value loaded */
202 "stdcx. %0,0,%1\n" /* store conditional */
203 "bne- 1b\n" /* retry if lost reservation */
206 : "r"(addr
), "r"(val
)
213 /* generate an illegal instruction. Cannot catch this with linker tricks
214 * when optimizations are disabled. */
215 __asm__
__volatile__(ILLEGAL_INSTR
);
220 #define uatomic_add_return(addr, v) \
221 ((__typeof__(*(addr))) _uatomic_add_return((addr), \
222 (unsigned long)(v), \
229 #include <urcu/uatomic_generic.h>
231 #endif /* _URCU_ARCH_UATOMIC_PPC_H */
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