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ec4e58a3 MD |
1 | #ifndef _URCU_ARCH_UATOMIC_PPC_H |
2 | #define _URCU_ARCH_UATOMIC_PPC_H | |
0114ba7f MD |
3 | |
4 | /* | |
5 | * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved. | |
6 | * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved. | |
7 | * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P. | |
8 | * Copyright (c) 2009 Mathieu Desnoyers | |
9 | * | |
10 | * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED | |
11 | * OR IMPLIED. ANY USE IS AT YOUR OWN RISK. | |
12 | * | |
13 | * Permission is hereby granted to use or copy this program | |
14 | * for any purpose, provided the above notices are retained on all copies. | |
15 | * Permission to modify the code and to distribute modified code is granted, | |
16 | * provided the above notices are retained, and a notice that the code was | |
17 | * modified is included with the above copyright notice. | |
18 | * | |
ec4e58a3 | 19 | * Code inspired from libuatomic_ops-1.2, inherited in part from the |
0114ba7f MD |
20 | * Boehm-Demers-Weiser conservative garbage collector. |
21 | */ | |
22 | ||
ec4e58a3 | 23 | #include <urcu/compiler.h> |
b46b23cb | 24 | #include <urcu/system.h> |
1315d277 | 25 | |
36bc70a8 MD |
26 | #ifdef __cplusplus |
27 | extern "C" { | |
28 | #endif | |
29 | ||
bcf80111 SM |
30 | #ifndef __SIZEOF_LONG__ |
31 | #ifdef __powerpc64__ | |
32 | #define __SIZEOF_LONG__ 8 | |
33 | #else | |
34 | #define __SIZEOF_LONG__ 4 | |
35 | #endif | |
36 | #endif | |
37 | ||
701dd8de SAS |
38 | #ifdef __NO_LWSYNC__ |
39 | #define LWSYNC_OPCODE "sync\n" | |
40 | #else | |
41 | #define LWSYNC_OPCODE "lwsync\n" | |
42 | #endif | |
43 | ||
0114ba7f MD |
44 | #ifndef BITS_PER_LONG |
45 | #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) | |
46 | #endif | |
47 | ||
e7061ad2 | 48 | #define ILLEGAL_INSTR ".long 0xd00d00" |
0114ba7f | 49 | |
0114ba7f MD |
50 | /* |
51 | * Using a isync as second barrier for exchange to provide acquire semantic. | |
ec4e58a3 | 52 | * According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly |
0114ba7f MD |
53 | * explicit that this also has acquire semantics." |
54 | * Derived from AO_compare_and_swap(), but removed the comparison. | |
55 | */ | |
56 | ||
f689dcbc MD |
57 | /* xchg */ |
58 | ||
da1c1635 | 59 | static inline __attribute__((always_inline)) |
ec4e58a3 | 60 | unsigned long _uatomic_exchange(void *addr, unsigned long val, int len) |
0114ba7f | 61 | { |
f689dcbc MD |
62 | switch (len) { |
63 | case 4: | |
64 | { | |
65 | unsigned int result; | |
66 | ||
67 | __asm__ __volatile__( | |
701dd8de | 68 | LWSYNC_OPCODE |
f689dcbc MD |
69 | "1:\t" "lwarx %0,0,%1\n" /* load and reserve */ |
70 | "stwcx. %2,0,%1\n" /* else store conditional */ | |
71 | "bne- 1b\n" /* retry if lost reservation */ | |
72 | "isync\n" | |
73 | : "=&r"(result) | |
74 | : "r"(addr), "r"(val) | |
75 | : "memory", "cc"); | |
76 | ||
77 | return result; | |
78 | } | |
79 | #if (BITS_PER_LONG == 64) | |
80 | case 8: | |
81 | { | |
82 | unsigned long result; | |
83 | ||
84 | __asm__ __volatile__( | |
701dd8de | 85 | LWSYNC_OPCODE |
f689dcbc MD |
86 | "1:\t" "ldarx %0,0,%1\n" /* load and reserve */ |
87 | "stdcx. %2,0,%1\n" /* else store conditional */ | |
88 | "bne- 1b\n" /* retry if lost reservation */ | |
89 | "isync\n" | |
90 | : "=&r"(result) | |
91 | : "r"(addr), "r"(val) | |
92 | : "memory", "cc"); | |
93 | ||
94 | return result; | |
95 | } | |
96 | #endif | |
97 | } | |
98 | /* generate an illegal instruction. Cannot catch this with linker tricks | |
99 | * when optimizations are disabled. */ | |
100 | __asm__ __volatile__(ILLEGAL_INSTR); | |
101 | return 0; | |
0114ba7f MD |
102 | } |
103 | ||
ec4e58a3 MD |
104 | #define uatomic_xchg(addr, v) \ |
105 | ((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \ | |
da1c1635 | 106 | sizeof(*(addr)))) |
f689dcbc | 107 | /* cmpxchg */ |
0114ba7f | 108 | |
da1c1635 | 109 | static inline __attribute__((always_inline)) |
ec4e58a3 | 110 | unsigned long _uatomic_cmpxchg(void *addr, unsigned long old, |
f689dcbc | 111 | unsigned long _new, int len) |
0114ba7f | 112 | { |
f689dcbc MD |
113 | switch (len) { |
114 | case 4: | |
115 | { | |
116 | unsigned int old_val; | |
117 | ||
118 | __asm__ __volatile__( | |
701dd8de | 119 | LWSYNC_OPCODE |
f689dcbc MD |
120 | "1:\t" "lwarx %0,0,%1\n" /* load and reserve */ |
121 | "cmpd %0,%3\n" /* if load is not equal to */ | |
122 | "bne 2f\n" /* old, fail */ | |
123 | "stwcx. %2,0,%1\n" /* else store conditional */ | |
124 | "bne- 1b\n" /* retry if lost reservation */ | |
125 | "isync\n" | |
126 | "2:\n" | |
e72f4937 | 127 | : "=&r"(old_val) |
f689dcbc MD |
128 | : "r"(addr), "r"((unsigned int)_new), |
129 | "r"((unsigned int)old) | |
130 | : "memory", "cc"); | |
131 | ||
132 | return old_val; | |
133 | } | |
134 | #if (BITS_PER_LONG == 64) | |
135 | case 8: | |
136 | { | |
137 | unsigned long old_val; | |
138 | ||
139 | __asm__ __volatile__( | |
701dd8de | 140 | LWSYNC_OPCODE |
f689dcbc MD |
141 | "1:\t" "ldarx %0,0,%1\n" /* load and reserve */ |
142 | "cmpd %0,%3\n" /* if load is not equal to */ | |
143 | "bne 2f\n" /* old, fail */ | |
144 | "stdcx. %2,0,%1\n" /* else store conditional */ | |
145 | "bne- 1b\n" /* retry if lost reservation */ | |
146 | "isync\n" | |
147 | "2:\n" | |
148 | : "=&r"(old_val), | |
149 | : "r"(addr), "r"((unsigned long)_new), | |
150 | "r"((unsigned long)old) | |
151 | : "memory", "cc"); | |
152 | ||
153 | return old_val; | |
154 | } | |
155 | #endif | |
156 | } | |
157 | /* generate an illegal instruction. Cannot catch this with linker tricks | |
158 | * when optimizations are disabled. */ | |
159 | __asm__ __volatile__(ILLEGAL_INSTR); | |
160 | return 0; | |
0114ba7f MD |
161 | } |
162 | ||
da1c1635 | 163 | |
ec4e58a3 MD |
164 | #define uatomic_cmpxchg(addr, old, _new) \ |
165 | ((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\ | |
da1c1635 MD |
166 | (unsigned long)(_new), \ |
167 | sizeof(*(addr)))) | |
f689dcbc | 168 | |
ec4e58a3 | 169 | /* uatomic_add_return */ |
0114ba7f | 170 | |
da1c1635 | 171 | static inline __attribute__((always_inline)) |
ec4e58a3 | 172 | unsigned long _uatomic_add_return(void *addr, unsigned long val, |
f689dcbc | 173 | int len) |
0114ba7f MD |
174 | { |
175 | switch (len) { | |
f689dcbc MD |
176 | case 4: |
177 | { | |
178 | unsigned int result; | |
179 | ||
180 | __asm__ __volatile__( | |
701dd8de | 181 | LWSYNC_OPCODE |
f689dcbc MD |
182 | "1:\t" "lwarx %0,0,%1\n" /* load and reserve */ |
183 | "add %0,%2,%0\n" /* add val to value loaded */ | |
184 | "stwcx. %0,0,%1\n" /* store conditional */ | |
185 | "bne- 1b\n" /* retry if lost reservation */ | |
186 | "isync\n" | |
187 | : "=&r"(result) | |
188 | : "r"(addr), "r"(val) | |
189 | : "memory", "cc"); | |
190 | ||
191 | return result; | |
192 | } | |
0114ba7f | 193 | #if (BITS_PER_LONG == 64) |
f689dcbc MD |
194 | case 8: |
195 | { | |
196 | unsigned long result; | |
197 | ||
198 | __asm__ __volatile__( | |
701dd8de | 199 | LWSYNC_OPCODE |
f689dcbc MD |
200 | "1:\t" "ldarx %0,0,%1\n" /* load and reserve */ |
201 | "add %0,%2,%0\n" /* add val to value loaded */ | |
202 | "stdcx. %0,0,%1\n" /* store conditional */ | |
203 | "bne- 1b\n" /* retry if lost reservation */ | |
204 | "isync\n" | |
205 | : "=&r"(result) | |
206 | : "r"(addr), "r"(val) | |
207 | : "memory", "cc"); | |
208 | ||
209 | return result; | |
210 | } | |
0114ba7f MD |
211 | #endif |
212 | } | |
213 | /* generate an illegal instruction. Cannot catch this with linker tricks | |
214 | * when optimizations are disabled. */ | |
215 | __asm__ __volatile__(ILLEGAL_INSTR); | |
216 | return 0; | |
217 | } | |
218 | ||
da1c1635 | 219 | |
ec4e58a3 MD |
220 | #define uatomic_add_return(addr, v) \ |
221 | ((__typeof__(*(addr))) _uatomic_add_return((addr), \ | |
da1c1635 MD |
222 | (unsigned long)(v), \ |
223 | sizeof(*(addr)))) | |
f689dcbc | 224 | |
36bc70a8 MD |
225 | #ifdef __cplusplus |
226 | } | |
227 | #endif | |
228 | ||
8760d94e PB |
229 | #include <urcu/uatomic_generic.h> |
230 | ||
ec4e58a3 | 231 | #endif /* _URCU_ARCH_UATOMIC_PPC_H */ |